4 at 9:14 PM Alistair Francis
> wrote:
> >
> > On Mon, May 13, 2024 at 9:05 PM Alexey Baturo
> wrote:
> > >
> > > Hi,
> > >
> > > > Hi, any change from v0.8 to v1.0?
> > > Not in the patches that were sent. I'd still suggest applyin
ei wrote:
> >
> >
> > On 2024/5/11 18:10, Alexey Baturo wrote:
> > > From: Alexey Baturo
> > >
> > > Hi,
> > >
> > > It looks like Pointer Masking spec has reached v1.0 and been frozen,
> > > rebasing on riscv-to-apply.next br
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 13 +
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
Acked-by: Alistair Francis
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e350e9bd8..b3b3a6275f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 5
target/riscv/cpu_helper.c | 58 +++
2 files changed, 63 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alexey Baturo
Hi,
It looks like Pointer Masking spec has reached v1.0 and been frozen,
rebasing on riscv-to-apply.next branch and resubmitting patches.
Thanks.
[v8]:
Rebasing patches on current qemu branch and resubmitting them.
[v7]:
I'm terribly sorry, but previous rebase went
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 10 +++---
target/riscv/pmp.c
;
g_free(elem);
and aren't problematic.
Signed-off-by: Alexey Dobriyan
---
hopefully better changelog.
use "if (out_num < 1)" so that discard doesn't calculate iov length
hw/net/virtio-net.c | 18 --
1 file changed, 12 insertions(+), 6 deletio
aiting
for TX to complete, TX complete hook is _not_ called and
assert(async_tx.elem) is eventually triggered.
The fix is to discard such phantom packets in virtio_net_flush_tx().
Signed-off-by: Alexey Dobriyan
---
hw/net/virtio-net.c | 18 --
1 file changed, 12 insertions(+), 6
On Tue, Apr 09, 2024 at 12:41:39PM -0400, Michael S. Tsirkin wrote:
> On Tue, Apr 09, 2024 at 07:37:04PM +0300, Alexey Dobriyan wrote:
> > On Tue, Apr 09, 2024 at 02:51:38AM -0400, Michael S. Tsirkin wrote:
> > > On Fri, Apr 05, 2024 at 02:20:15PM +0300, Alexey Dobriyan wrote:
On Tue, Apr 09, 2024 at 02:51:38AM -0400, Michael S. Tsirkin wrote:
> On Fri, Apr 05, 2024 at 02:20:15PM +0300, Alexey Dobriyan wrote:
> > Don't send zero length packets in virtio_net_flush_tx().
> >
> > Reproducer from https://gitlab.com/qemu-project/qemu/-/issues/1451
>
On Mon, Apr 08, 2024 at 03:26:35PM +0800, Jason Wang wrote:
> On Fri, Apr 5, 2024 at 7:22 PM Alexey Dobriyan
> wrote:
> >
> > Don't send zero length packets in virtio_net_flush_tx().
> >
> > Reproducer from https://gitlab.com/qemu-project/qemu/-/issues/1451
>
rrible because queue is being destroyed, nothing has been sent,
nobody is waiting for TX to complete and assert it triggered.
Signed-off-by: Alexey Dobriyan
---
hw/net/virtio-net.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 73c69f3d0a..9e3bf6c5c5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 13 +
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 58 +++
2 files changed, 62 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 10 +++---
target/riscv/pmp.c
From: Alexey Baturo
Hi,
Rebasing patches on current qemu branch and resubmitting them.
Thanks.
[v7]:
I'm terribly sorry, but previous rebase went wrong and somehow I missed it.
This time I double-checked rebased version.
This patch series is properly rebased on
https://github.com/alistair23
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
Acked-by: Alistair Francis
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ded84f2e09..23d1692b59 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
Acked-by: Alistair Francis
From: Alexey Baturo
Hi,
I'm terribly sorry, but previous rebase went wrong and somehow I missed it.
This time I double-checked rebased version.
This patch series is properly rebased on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Thanks
[v6]:
This patch series is rebased
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 58 +++
2 files changed, 62 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 13 +
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 10 +++---
target/riscv/pmp.c
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
Acked-by: Alistair Francis
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 13 +
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target
From: Alexey Baturo
Hi,
This patch series is rebased on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Thanks
[v5]:
This patch series targets Zjpm v0.8 extension.
The spec itself could be found here:
https://github.com/riscv/riscv-j-extension/blob
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 58 +++
2 files changed, 62 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 10 +++---
target/riscv/pmp.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ded84f2e09..23d1692b59 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 58 +++
2 files changed, 62 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c9bed5c9fc..1c8979c1c8 100644
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 13 +
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d8de1f1890..bf431ab728 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,6 +153,9 @@ const
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
Acked-by: Alistair Francis
From: Alexey Baturo
Hi,
This patch series targets Zjpm v0.8 extension.
The spec itself could be found here:
https://github.com/riscv/riscv-j-extension/blob/8088461d8d66a7676872b61c908cbeb7cf5c5d1d/zjpm-spec.pdf
This patch series is updated after the suggested comments:
- add &q
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 10 +++---
target/riscv/pmp.c
Hi,
Having the feature to run binaries with pointer masking on qemu-user is
really nice, but I see this patch series as an initial support.
Obviously there'll be more patches and fixes for pointer masking as soon as
arch tests are ready.
I suggest supporting qemu-user in the next patches, but
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 10 +++---
target/riscv/pmp.c | 13 ++---
target
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 58 +++
2 files changed, 62 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c9bed5c9fc..1c8979c1c8 100644
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 13 +
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target
From: Alexey Baturo
Hi,
Patch series updated after the suggested comments:
- removed J-letter extension as it's unused
- renamed and fixed function to detect if address should be sign-extended
- zeroed unused context variables and moved computation logic to another patch
- bumped pointer
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d8de1f1890..44ebd80aba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,6 +153,9 @@ const
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c
I think you're right, thanks.
I'll add a check for M-mode as well and I guess I'll have to rename the
function.
Any ideas on the proper and self-describing name?
Thanks
пт, 5 янв. 2024 г. в 03:46, Deepak Gupta :
> On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo
> wrote:
> >
> +addr = addr << pmlen;
> +if (signext) {
> +addr = (target_long)addr >> pmlen;
> +} else {
> +addr = addr >> pmlen;
Could you please elaborate a bit more on your concern here?
I believe this code works as intended: https://godbolt.org/z/b9c7na13a
Thanks
пт, 5 янв.
Sure, I would do it in the next updated series.
пт, 5 янв. 2024 г. в 08:04, Alistair Francis :
> On Thu, Jan 4, 2024 at 6:33 AM Alexey Baturo
> wrote:
> >
> > From: Alexey Baturo
> >
> > Zjpm v0.8 is almost frozen and it's much simplier compared to the
> ex
I might be wrong here, but right now J in MISA is unused.
I think the J-letter extension is still a thing, but current extensions
like Zjpm and Zjid follow the Z ext scheme.
Do you think it should be removed?
пт, 5 янв. 2024 г. в 08:28, Alistair Francis :
> On Thu, Jan 4, 2024 at 4:58 AM Ale
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 6 --
target/riscv/pmp.c | 13 ++---
target
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 11 +++
3 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c607a94bba..4df160494f 100644
From: Alexey Baturo
Hi,
There patches are updated after Richard's comments:
- moved new tb flags to the end
- used tcg_gen_(s)extract to get the final address
- properly handle CONFIG_USER_ONLY
Thanks
[v2]:
As per Richard's suggestion I made pmm field part of tb_flags.
It allowed to get rid
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 54 +++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bd379ee653..c607a94bba 100644
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 12
target/riscv/vector_helper.c | 12
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8ac2819fa5..457de381c7
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e6571ce99..13389ddc55 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,6 +153,9 @@ const
and I agree we could do it as part of future clean up.
Thanks, Richard
пт, 29 дек. 2023 г. в 02:33, Richard Henderson :
> On 12/24/23 15:48, Alexey Baturo wrote:
> > From: Alexey Baturo
> >
> > Signed-off-by: Alexey Baturo
> > ---
> > target/riscv/cpu.h
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 15 +--
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 6 --
target/riscv/pmp.c | 13 ++---
target
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 54 +++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bd379ee653..c607a94bba 100644
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e6571ce99..13389ddc55 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,6 +153,9 @@ const
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 23 +--
target/riscv/vector_helper.c | 10 ++
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1eb501e0d3
.
Compared to the original implementation with explicit base and mask CSRs, we
now only have
several fixed options for number of masked bits which are set using existing
CSRs.
The changes have been tested with handwritten assembly tests and LLVM HWASAN
test suite.
Thanks
Alexey Baturo (6
e 2 extracted bits. Is it ok with you?
Thanks
пт, 22 дек. 2023 г. в 01:49, Richard Henderson :
> On 12/21/23 21:40, Alexey Baturo wrote:
> > From: Alexey Baturo
> >
> > Signed-off-by: Alexey Baturo
> > ---
> > target/riscv/cpu.h| 19 +--
2_t) * ac,
sizeof(mem0_end_copy));
+ mem0_end = be64_to_cpu(mem0_end_copy);
mem0_end = ldq_be_p(mem0_reg + sizeof(uint32_t) * ac);
+1 for ldq_be_p(). Or read lo 32bit chunks and combine. Thanks,
r~
--
Alexey
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 19 +--
target/riscv/cpu_helper.c | 4
target/riscv/translate.c | 10 ++
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 49 +++
2 files changed, 51 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2099168950..9a8e5bc022 100644
From: Alexey Baturo
Hi all,
It looks like Zjpm v0.8 is almost frozen and we don't expect it change
drastically anymore.
Compared to the original implementation with explicit base and mask CSRs, we
now only have
several fixed options for number of masked bits which are set using existing
CSRs
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c| 9 +
target/riscv/cpu_helper.c | 1 +
target/riscv/csr.c| 4
target/riscv/machine.c| 1 +
target/riscv/pmp.c| 1 +
5 files changed, 16 insertions(+)
diff --git a/target/riscv
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 6 --
target/riscv/pmp.c | 13 ++---
target
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 21 +++--
target/riscv/vector_helper.c | 7 +++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4c0d526b58
Hi Alistair,
Thanks for the lightning fast reply!
Could you please tell who should bump those numbers and to what values?
Do you think I could submit this patch series for the review?
Thanks
пн, 18 дек. 2023 г. в 06:11, Alistair Francis :
> On Sat, Dec 16, 2023 at 11:52 PM Alexey Bat
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 49 +++
2 files changed, 51 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2099168950..9a8e5bc022 100644
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 21 +++--
target/riscv/vector_helper.c | 7 +++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4c0d526b58
From: Alexey Baturo
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++
target/riscv/machine.c | 6 --
target/riscv/pmp.c | 13 ++---
target
From: Alexey Baturo
Hi all,
It looks like Zjpm v0.8 is almost frozen and we don't expect it change
drastically anymore.
Compared to the original implementation with explicit base and mask CSRs, we
now only have
several fixed options for number of masked bits which are set using existing
CSRs
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c| 9 +
target/riscv/cpu_helper.c | 1 +
target/riscv/csr.c| 4
target/riscv/machine.c| 1 +
target/riscv/pmp.c| 1 +
5 files changed, 16 insertions(+)
diff --git a/target/riscv
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 19 +--
target/riscv/cpu_helper.c | 4
target/riscv/translate.c | 10 ++
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
to fetch changes up to b6838bf9c01c32bfecd5c446c98e788bbfd467d9:
pseries: Update SLOF firmware image (2023-11-21 19:11:31 +1100)
Alexey Kardashevskiy (1):
pseries: Update SLOF firmware image
pc-bios/README | 2 +-
pc
for you to fetch changes up to b4f872c6bcbf71f60326988c76b240318c51bd16:
pseries: Update SLOF firmware image (2023-09-18 19:14:44 +1000)
Alexey Kardashevskiy (1):
pseries: Update SLOF firmware image
pc-bios/README | 2
@@ F: include/hw/pci-host/mv64361.h
Virtual Open Firmware (VOF)
M: Alexey Kardashevskiy
-R: Cédric Le Goater
-R: Daniel Henrique Barboza
R: David Gibson
-R: Greg Kurz
L: qemu-...@nongnu.org
-S: Maintained
+S: Odd Fixes
F: hw/ppc/spapr_vof*
F: hw/ppc/vof*
F: include/hw/ppc/vof
Signed-off-by: Alexey Baturo
---
target/riscv/cpu_bits.h | 6 ++
target/riscv/csr.c | 8
target/riscv/pmp.c | 5 +
target/riscv/pmp.h | 12 +++-
4 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 6 ++--
target/riscv/cpu_helper.c | 58 +++
2 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 17d0088cb4..c87c4f26a2 100644
--- a/target
.
Thanks
Alexey Baturo (8):
target/riscv: Remove obsolete pointer masking extension code
target/riscv: Add new S{sn,mn,m}jpm extensions as part of Zjpm v0.6.1
target/riscv: Add new bits in CSRs for Zjpm 0.6.1
Add enum with maximum ignored bits depending on privilege level for
Zjpm v0.6.1
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/machine.c | 6 --
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f937820976..af8f16b94f 100644
--- a/target/riscv
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 21 +++--
target/riscv/vector_helper.c | 7 +++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3434ba58b6..4aa0e2b9e1 100644
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 19 +--
target/riscv/cpu_helper.c | 4
target/riscv/translate.c | 10 ++
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 25fe60476b
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 12 --
target/riscv/cpu.h | 30 +---
target/riscv/cpu_bits.h | 82 -
target/riscv/cpu_helper.c| 52 --
target/riscv/csr.c | 326 ---
target/riscv/machine.c
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c| 1 +
target/riscv/cpu_helper.c | 1 +
target/riscv/csr.c| 4
target/riscv/machine.c| 1 +
target/riscv/pmp.c| 1 +
5 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 62dabfa207..25fe60476b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -88,6 +88,16 @@ typedef enum
t; DisplayOptions *opts)
> assert(opts->type == DISPLAY_TYPE_GTK);> s->opts = opts;
's' is already used here.
>
> +*s = g_malloc0(sizeof(*s));
s = g_malloc0(sizeof(*s));
> theme = gtk_icon_theme_get_default();
> dir = get_relocated_path(CONFIG_QE
1 - 100 of 4549 matches
Mail list logo
