Signed-off-by: Alistair Francis
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 662ec47246..9ba30cec8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2173,6 +2173,7 @@ Generic Loader
M: Alistair Francis
S: Maintained
F: hw/core/generic-loade
From: Weiwei Li
- Zmmul is ratified and is now version 1.0
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220710101546.3907-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertion
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 10 ++
target/
From: Weiwei Li
Add umode/umode32 predicate for mcounteren, menvcfg/menvcfgh
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-5-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/ri
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Alistair Francis
Signed-off-by: Jaso
From: Frédéric Pétrot
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction that does not change processor state.
For rv128c right shifts, the 6-bit shamt is in addition sign extended to
7 bits.
Signed-off-by: Frédéric Pétrot
Reviewed-by: W
From: Weiwei Li
Add check for the implicit dependence between H and S
Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32 based on section 8.6.1 of riscv-privileged spec
(draft-20220717)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Andre
From: Anup Patel
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e9 ("target/riscv: Add isa extens
From: Dao Lu
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner
Reviewed-by: Alistair Francis
Signed-off-by: Dao Lu
Message-Id: <20220725034728.2620750-2-da...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cp
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 3 +++
target/riscv/in
From: Weiwei Li
There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <2022071813
From: Daniel Henrique Barboza
The 'fdt' param is not being used in riscv_setup_rom_reset_vec().
Simplify the API by removing it. While we're at it, remove the redundant
'return' statement at the end of function.
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Bin Meng
Cc: Vijai Kumar K
Signed-of
From: Alexey Baturo
Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN")
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-Id: <20220717101543.478533-2-space.monkey.deliv...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 2 +-
1
From: Weiwei Li
Fix the lines with over 80 characters
Fix the lines which are obviously misalgined with other lines in the
same group
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-4-liwei...@is
From: Anup Patel
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Acked-by: dramforever
Message-Id: <20220630061
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 7 +++
target/risc
From: Conor Dooley
When optional AIA PLIC support was added the to the virt machine, the
address cells property was removed leading the issues with dt-validate
on a dump from the virt machine:
/stuff/qemu/qemu.dtb: plic@c00: '#address-cells' is a required property
From schema:
/stuff
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 26 --
1
From: Weiwei Li
Add check for "H depends on an I base integer ISA with 32 x registers"
which is stated at the beginning of chapter 8 of the riscv-privileged
spec(draft-20220717)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Mess
The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80:
Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into
staging (2022-09-06 08:31:24 -0400)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply
From: Atish Patra
Historically, The mtime/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.
Move them to the ACLINT device. This also emulates the real hardware
more closely.
Reviewed-by: Anup Patel
Reviewed-by
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 11 +++
target
From: Weiwei Li
Just add 1 to the effective privledge level when in HS mode, then reuse
the check of 'effective_priv < csr_priv' in riscv_csrrw_check to replace
the privilege level related check in hmode. Then, hmode will only check
whether H extension is supported.
When accessing Hypervior CSRs
From: Bin Meng
Upgrade OpenSBI from v1.0 to v1.1 and the pre-built bios images.
The v1.1 release includes the following commits:
5b99603 lib: utils/ipi: Fix size check in aclint_mswi_cold_init()
6dde435 lib: utils/sys: Extend HTIF library to allow custom base address
8257262 platform: sifive_fu
From: Atish Patra
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to lever
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 35 +--
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 26 +++
From: "Yueh-Ting (eop) Chen"
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are
From: eopXD
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibi
From: Bin Meng
Since commit fbf43c7dbf18 ("target/riscv: enable riscv kvm accel"),
KVM accelerator is supported on RISC-V. Let's document it.
Signed-off-by: Bin Meng
Reviewed-by: Thomas Huth
Reviewed-by: Alistair Francis
Message-Id: <20220719082635.3741878-1-bin.m...@windriver.com>
Signed-off
From: Weiwei Li
Normally, riscv_csrrw_check is called when executing Zicsr instructions.
And we can only do access control for existed CSRs. So the priority of
CSR related check, from highest to lowest, should be as follows:
1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if no
From: Atish Patra
With .min_priv_version, additiona priv version check is uncessary
for mcountinhibit read/write functions.
Reviewed-by: Heiko Stuebner
Tested-by: Heiko Stuebner
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220816232321.558250-7-ati...@rivosinc.com>
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 26 +++
From: Conor Dooley
The reset and poweroff features of the syscon were originally added to
top level, which is a valid path for a syscon subnode. Subsequently a
reorganisation was carried out while implementing NUMA in which the
subnodes were moved into the /soc node. As /soc is a "simple-bus", th
From: Anup Patel
The arch review of AIA spec is completed and we now have official
extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
AIA CSRs).
Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32
From: Rahul Pathak
XVentanaCondOps is Ventana custom extension. Add
its extension entry in the ISA Ext array
Signed-off-by: Rahul Pathak
Reviewed-by: Alistair Francis
Message-id: 20220816045408.1231135-1-rpat...@ventanamicro.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1
From: Wilfred Mallawa
The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies which
From: Conor Dooley
"platform" is not a valid name for a bus node in dt-schema, so warnings
can be see in dt-validate on a dump of the riscv virt dtb:
/stuff/qemu/qemu.dtb: platform@400: $nodename:0: 'platform@400' does
not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?
From: Atish Patra
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221357.41070-3-ati...@riv
From: Conor Dooley
Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot
entirely is probably not advisable, but it does at least show signs of
life. Recent Linux kernel versions make use of peripherals that are
missing definitions in QEMU and lead to kernel panics. These issues
From: Atish Patra
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Reviewed-by: Alistair Francis
Signed-off
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Reviewed-by: Alistair Francis
Tested-by: Heiko Stuebner
Signed-off-by: Atish Patra
Signed-off-b
From: Conor Dooley
"uart" is not a node name that complies with the dt-schema.
Change the node name to "serial" to ix warnings seen during
dt-validate on a dtbdump of the virt machine such as:
/stuff/qemu/qemu.dtb: uart@1000: $nodename:0: 'uart@1000' does not
match '^serial(@.*)?$'
From: Atish Patra
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Re
From: Atish Patra
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Acked-by:
From: Atish Patra
The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221701.41932-6-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
targ
Instead of using our properties to set a config value which then might
be used to set the resetvec (depending on your timing), let's instead
just set the resetvec directly in the env struct.
This allows us to set the reset vec from the command line with:
-global driver=riscv.hart_array,propert
The resetvec for the OpenTitan machine ended up being set to an out of
date value, so let's fix that and bump it to the correct start address
(after the boot ROM)
Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version"
Signed-off-by: Alistair Francis
---
hw/riscv/opentitan.c | 2 +-
1
The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
ROM flow. This series makes it more configurguable from the command line
and fixes the default.
Alistair Francis (3):
target/riscv: Set the CPU resetvec directly
hw/riscv: opentitan: Fixup resetvec
hw/riscv: opentitan: E
On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
QEMU we don't run the ROM code and instead just jump to the next stage.
This means we need to be a little more flexible about what the resetvec
is.
This patch allows us to set the resetvec from the command line with
something
From: Mikhail Tyutin
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
instructions
Signed-off-by: Mikhail Tyutin
Reviewed-by: Alistair Francis
Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc38...@yadro.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 19 ++--
On Tue, Jun 25, 2024 at 9:47 PM wrote:
>
> From: Frank Chang
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
> ordering requiremen
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