[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Acked-by: Alistair Francis ---

[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger

According to RISC-V Debug specification ratified version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege

[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to

[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

From: Alvin Chang via According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds

[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger

From: Alvin Chang via We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Acked

[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint

From: Alvin Chang via We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels

[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger

According to RISC-V Debug specification ratified version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege

[PATCH v5 3/4] target/riscv: Apply modularized matching conditions for watchpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v5 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Acked-by: Alistair Francis ---

[PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger

According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to

[PATCH v5 2/4] target/riscv: Apply modularized matching conditions for breakpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger

According to RISC-V Debug specification ratified version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege

[PATCH v4 1/4] target/riscv: Add functions for common matching conditions of trigger

According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to

[PATCH v4 3/4] target/riscv: Apply modularized matching conditions for watchpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger

According to RISC-V Debug specification ratified version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege

[PATCH v4 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2 +- 1

[PATCH v4 2/4] target/riscv: Apply modularized matching conditions for breakpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v3 0/4] RISC-V: Modularize common match conditions for trigger

According to latest RISC-V Debug specification version 1.0 [1], the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege levels of type 2/3/6 triggers by implementing functions

[PATCH v3 2/4] target/riscv: Apply modularized matching conditions for breakpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v3 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2 +- 1

[PATCH v3 3/4] target/riscv: Apply modularized matching conditions for watchpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v3 1/4] target/riscv: Add functions for common matching conditions of trigger

According to RISC-V Debug specification version 1.0 [1], there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to prepare the common matching conditions for the type 2/3/6 triggers. For

[PATCH v2 1/4] target/riscv: Add functions for common matching conditions of trigger

According to RISC-V Debug specification, there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to prepare the common matching conditions for the type 2/3/6 triggers. For now, we just

[PATCH v2 0/4] RISC-V: Modularize common match conditions for trigger

According to RISC-V Debug specification, the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege levels of type 2/3/6 triggers by implementing functions trigger_common_match() and

[PATCH v2 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2 +- 1

[PATCH v2 3/4] target/riscv: Apply modularized matching conditions for watchpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH v2 2/4] target/riscv: Apply modularized matching conditions for breakpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH 1/4] target/riscv: Add functions for common matching conditions of trigger

According to RISC-V Debug specification, there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to prepare the common matching conditions for the type 2/3/6 triggers. For now, we just

[PATCH 0/4] RISC-V: Modularize common match conditions for trigger

According to RISC-V Debug specification, the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege levels of type 2/3/6 triggers by implementing functions trigger_common_match() and

[PATCH 3/4] target/riscv: Apply modularized matching conditions for watchpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH 2/4] target/riscv: Apply modularized matching conditions for breakpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6

[PATCH 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2 +- 1

[PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed

The RISC-V debug specification defines the following operation for CSR tcontrol when "mret" is executed: - tcontrol.MTE is set to the value of tcontrol.MPTE This commit implements the above operation into helper_mret(). Note that from tech-debug mailing list:

[PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module

The RISC-V debug specification defines an optional CSR "tcontrol" within the trigger module. This commit adds its read/write operations and related bit-field definitions. Signed-off-by: Alvin Chang --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c |

[PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode

>From the RISC-V debug specification, it defines the following operations for CSR tcontrol when any trap into M-mode is taken: 1. tcontrol.MPTE is set to the value of tcontrol.MTE 2. tcontrol.MTE is set to 0 This commit implements the above operations into riscv_cpu_do_interrupt().

[PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec

The RISC-V Debug specification defines CSR "tcontrol" in the trigger module: https://github.com/riscv/riscv-debug-spec This series implements it and the related operations. Alvin Chang (4): target/riscv: Add CSR tcontrol of debug trigger module target/riscv: Reset CSR tcontrol when the

[PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets

When the trigger module resets, reset the value of CSR tcontrol as zero. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e30d99cc2f..e3832a643e 100644 --- a/target/riscv/debug.c +++

[PATCH v2] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

The debug Sdtrig extension defines an CSR "mcontext". This commit implements its predicate and read/write operations into CSR table. Its value is reset as 0 when the trigger module is reset. Signed-off-by: Alvin Chang --- Changes from v1: Remove dedicated cfg, always implement mcontext.

[PATCH] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

The debug Sdtrig extension defines an optional CSR "mcontext". Since it is optional, this commit adds new CPU configuration "ext_sdtrig_mcontext" and uses property "sdtrig_mcontext" to control whether it is implemented or not. Its predicate and read/write operations are also implemented into CSR

[PATCH v5] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

Current checks on writing pmpcfg for Smepmp follows Smepmp version 0.9.1. However, Smepmp specification has already been ratified, and there are some differences between version 0.9.1 and 1.0. In this commit we update the checks of writing pmpcfg to follow Smepmp version 1.0. When mseccfg.MML is