On Tue, Jun 13, 2023 at 05:58:54PM -0300, Daniel Henrique Barboza wrote:
> The isa_edata_arr[] is used by riscv_isa_string_ext() to create the
> riscv,isa DT attribute. isa_edata_arr[] is kept in sync with the TCG
> property vector riscv_cpu_extensions[], i.e. all TCG properties from
> this vector
>name, ret);
> +kvm_riscv_destroy_scratch_vcpu(kvmcpu);
> +exit(EXIT_FAILURE);
> +}
> +} else {
> +multi_ext_cfg->supported = true;
> +}
> +
> +kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
> +}
> +}
> +
> void kvm_riscv_init_user_properties(Object *cpu_obj)
> {
> RISCVCPU *cpu = RISCV_CPU(cpu_obj);
> @@ -540,6 +663,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj)
> kvm_riscv_add_cpu_user_properties(cpu_obj);
> kvm_riscv_init_machine_ids(cpu, );
> kvm_riscv_init_misa_ext_mask(cpu, );
> +kvm_riscv_init_multiext_cfg(cpu, );
>
> kvm_riscv_destroy_scratch_vcpu();
> }
> --
> 2.40.1
>
Reviewed-by: Andrew Jones
> +}
> +}
> +
> static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> {
> int i;
> @@ -630,8 +665,13 @@ int kvm_arch_init_vcpu(CPUState *cs)
>
> if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
> ret = kvm_vcpu_set_machine_ids(cpu, cs);
> +if (ret != 0) {
> +return ret;
> +}
> }
>
> +kvm_riscv_update_cpu_misa_ext(cpu, cs);
> +
> return ret;
> }
>
> --
> 2.40.1
>
Besides the commit message clarification and the code comment typo,
Reviewed-by: Andrew Jones
Thanks,
drew
for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) {
> +KVMCPUConfig *misa_cfg = _misa_ext_cfgs[i];
> +
> +object_property_add(cpu_obj, misa_cfg->name, "bool",
> + NULL,
> +kvm_cpu_set_misa_ext_cfg,
> +NULL, misa_cfg);
> +object_property_set_description(cpu_obj, misa_cfg->name,
> +misa_cfg->description);
> +}
> +}
> +
> static int kvm_riscv_get_regs_core(CPUState *cs)
> {
> int ret = 0;
> @@ -427,6 +502,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj)
> return;
> }
>
> +kvm_riscv_add_cpu_user_properties(cpu_obj);
> kvm_riscv_init_machine_ids(cpu, );
> kvm_riscv_init_misa_ext_mask(cpu, );
>
> --
> 2.40.1
>
Reviewed-by: Andrew Jones
extensions. For now doing just with MISA extensions is enough.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 44 ++--
> target/riscv/cpu.h | 22 +-
> 2 files c
Please add a commit message to all patches of the series.
Another comment below.
On Thu, Jun 08, 2023 at 12:23:11AM -0700, Tommy Wu wrote:
> Signed-off-by: Frank Chang
> Signed-off-by: Tommy Wu
> ---
> hw/riscv/riscv_hart.c | 21 +
> include/hw/riscv/riscv_hart.h
On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote:
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable in RISC-V, which are:
>
> =
On Wed, Jun 07, 2023 at 05:37:16PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 6/7/23 10:01, Andrew Jones wrote:
> > On Tue, May 30, 2023 at 04:46:23PM -0300, Daniel Henrique Barboza wrote:
> > > If we don't set a proper cbom_blocksize|cboz_blocksize in the FD
On Wed, Jun 07, 2023 at 04:59:02PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 6/7/23 08:48, Andrew Jones wrote:
> > On Tue, May 30, 2023 at 04:46:20PM -0300, Daniel Henrique Barboza wrote:
> > > Let's add KVM user properties for the multi-letter extensions that KVM
On Tue, May 30, 2023 at 04:46:23PM -0300, Daniel Henrique Barboza wrote:
> If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
> Linux Kernel will fail to detect the availability of the CBOM/CBOZ
> extensions, regardless of the contents of the 'riscv,isa' DT prop.
>
> The FDT is
> static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> {
> int i;
> @@ -829,6 +855,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
> }
>
> kvm_riscv_update_cpu_misa_ext(cpu, cs);
> +kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
>
> return ret;
> }
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
On Tue, May 30, 2023 at 04:46:21PM -0300, Daniel Henrique Barboza wrote:
> KVM is not using the same attributes as TCG, i.e. it doesn't use
> isa_edata_arr[]. Add a new kvm_riscv_isa_string_ext() helper that does
> basically the same thing, but using KVM internals instead.
>
> The decision to add
On Tue, May 30, 2023 at 04:46:19PM -0300, Daniel Henrique Barboza wrote:
> Our design philosophy with KVM properties can be resumed in two main
> decisions based on KVM interface availability and what the user wants to
> do:
>
> - if the user disables an extension that the host KVM module doesn't
On Tue, May 30, 2023 at 04:46:20PM -0300, Daniel Henrique Barboza wrote:
> Let's add KVM user properties for the multi-letter extensions that KVM
> currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
> svinval and svpbmt.
>
> As with the recently added MISA properties we're also
On Tue, May 30, 2023 at 04:46:18PM -0300, Daniel Henrique Barboza wrote:
> Using all TCG user properties in KVM is tricky. First because KVM
> supports only a small subset of what TCG provides, so most of the
> cpu->cfg flags do nothing for KVM.
>
> Second, and more important, we don't have a way
---
> 1 file changed, 23 insertions(+), 11 deletions(-)
>
Reviewed-by: Andrew Jones
a;
>
> +if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
> +ret = kvm_vcpu_set_machine_ids(cpu, cs);
> +}
> +
> return ret;
> }
>
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
KVM_REG_RISCV_CONFIG_REG(mimpid));
> +reg.addr = (uint64_t)>cfg.mimpid;
> +ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, );
> +if (ret != 0) {
> +error_report("Unable to retrieve mimpid from host, error %d", ret);
> +}
> }
>
> void kvm_riscv_init_user_properties(Object *cpu_obj)
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
c properties in the next patches as well.
>
> [1] target/arm/kvm.c, kvm_arm_create_scratch_host_vcpu()
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 4 ++
> target/riscv/kvm.c | 85 ++++
> target/riscv/kvm_riscv.h | 1 +
> 3 files changed, 90 insertions(+)
>
Reviewed-by: Andrew Jones
turn;
> +}
> +
> +cpu->cfg.marchid = value;
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -1893,6 +1928,10 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
>cpu_set_mimpid,
>NULL, NULL);
>
> +object_class_property_add(c, "marchid", "uint64", NULL,
> + cpu_set_marchid,
> + NULL, NULL);
> +
get?
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> --
> 2.40.1
>
>
Otherwise,
Reviewed-by: Andrew Jones
NULL, NULL);
>
> +object_class_property_add(c, "mimpid", "uint64", NULL,
> + cpu_set_mimpid,
> + NULL, NULL);
> +
Same, shouldn't we also define 'get' comment as the last patch.
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -1841,6 +1866,10 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
> cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
> cc->tcg_ops = _tcg_ops;
>
> +object_class_property_add(c, "mvendorid", "uint32", NULL,
> + cpu_set_mvendorid,
> + NULL, NULL);
> +
Shouldn't we provide a get function as well?
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> --
> 2.40.1
>
>
Otherwise,
Reviewed-by: Andrew Jones
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
> +g_free(sv_name);
> +}
>
> name = riscv_isa_string(cpu_ptr);
> qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
> --
> 2.40.1
>
>
Adding a sentence, like what I wrote above, to the commit message in order
to provide better justification might be nice, but either way
Reviewed-by: Andrew Jones
Thanks,
drew
On Fri, Jun 02, 2023 at 07:58:30PM -0700, Richard Henderson wrote:
> On 6/2/23 07:02, Andrew Jones wrote:
> > > +struct riscv_hwprobe {
> > > +int64_t key;
> > > +uint64_t value;
> > > +};
> >
> > The above is all uapi so Linux's arch/ri
On Fri, Jun 02, 2023 at 04:39:20PM +0200, Robbin Ehn wrote:
> On Fri, 2023-06-02 at 16:02 +0200, Andrew Jones wrote:
> > On Fri, Jun 02, 2023 at 11:41:11AM +0200, Robbin Ehn wrote:
...
> > > +#if defined(TARGET_RISCV)
> > > +case TARGET_NR_riscv_hwprobe:
> >
te(errp, local_err);
> +return;
> +}
> +
> +if (!riscv_running_KVM()) {
> +riscv_cpu_realize_features(dev, _err);
> +if (local_err != NULL) {
> +error_propagate(errp, local_err);
> +return;
> +}
> +}
>
> riscv_cpu_finalize_features(cpu, _err);
> if (local_err != NULL) {
> --
> 2.40.1
>
>
Otherwise,
Reviewed-by: Andrew Jones
On Fri, Jun 02, 2023 at 11:41:11AM +0200, Robbin Ehn wrote:
> This patch adds the new syscall for the
> "RISC-V Hardware Probing Interface"
> (https://docs.kernel.org/riscv/hwprobe.html).
>
> Signed-off-by: Robbin Ehn
> ---
> v1->v2: Moved to syscall.c
> ---
> linux-user/riscv/syscall32_nr.h |
On Fri, May 26, 2023 at 04:42:57AM -0400, Andrea Bolognani wrote:
> On Fri, May 26, 2023 at 10:34:36AM +0200, Andrew Jones wrote:
> > On Fri, May 26, 2023 at 03:49:11AM -0400, Andrea Bolognani wrote:
> > > So, are edk2 users the only ones who would (temporarily) need to
> &
On Fri, May 26, 2023 at 03:49:11AM -0400, Andrea Bolognani wrote:
> On Fri, May 26, 2023 at 08:39:07AM +0200, Andrew Jones wrote:
> > On Thu, May 25, 2023 at 11:03:52AM -0700, Andrea Bolognani wrote:
> > > With these patches applied, libvirt built from the master branch,
> >
On Thu, May 25, 2023 at 11:03:52AM -0700, Andrea Bolognani wrote:
> On Thu, May 25, 2023 at 10:18:00PM +0530, Sunil V L wrote:
> > This series improves the pflash usage in RISC-V virt machine with solutions
> > to
> > below issues.
> >
> > 1) Currently the first pflash is reserved for ROM/M-mode
sed 's/emulateion/emulation' <<<$SUBJECT
and for the whole series
sed 's/PTACH/PATCH/' <<<$SUBJECT
Thanks,
drew
On Fri, May 05, 2023 at 11:39:37AM +, Yong-Xuan Wang wrote:
> Remove M mode AIA devices when using KVM acceleration
>
> Signed-off-by: Yong-Xuan Wang
> Reviewed-by: Jim Shu
On Tue, Apr 11, 2023 at 08:43:49AM +0100, Alex Bennée wrote:
>
> Andrew Jones writes:
...
> > Someday mkstandalone could maybe learn how to build
> > a directory hierarchy using the group names, e.g.
> >
> > tests/mttcg/tlb/all_other
>
> So nodefault
On Tue, Apr 11, 2023 at 09:26:56AM +0100, Alex Bennée wrote:
>
> Andrew Jones writes:
>
> > On Tue, Mar 07, 2023 at 11:28:42AM +, Alex Bennée wrote:
> >> This adds a fairly brain dead torture test for TLB flushes intended
> >> for stressing the MTTCG QE
On Tue, Mar 07, 2023 at 11:28:38AM +, Alex Bennée wrote:
> I last had a go at getting these up-streamed at the end of 2021 so
> its probably worth having another go. From the last iteration a
> number of the groundwork patches did get merged:
>
> Subject: [kvm-unit-tests PATCH v9 0/9] MTTCG
On Tue, Mar 21, 2023 at 04:02:21PM +0100, Andrew Jones wrote:
...
> > +
> > +# TLB Torture Tests
> > +[tlbflush-code::all_other]
>
> It's better to use '-', '_', '.', or ',' than '::' because otherwise the
> standalone test will have a filename like tests/tlbfl
On Tue, Mar 07, 2023 at 11:28:43AM +, Alex Bennée wrote:
> This test has been written mainly to stress multi-threaded TCG behaviour
> but will demonstrate failure by default on real hardware. The test takes
> the following parameters:
>
> - "lock" use GCC's locking semantics
> - "atomic"
On Tue, Mar 07, 2023 at 11:28:42AM +, Alex Bennée wrote:
> This adds a fairly brain dead torture test for TLB flushes intended
> for stressing the MTTCG QEMU build. It takes the usual -smp option for
> multiple CPUs.
>
> By default it CPU0 will do a TLBIALL flush after each cycle. You can
>
-nogit
> --nogit-fallback 2>/dev/null
Should we also set the prefix for these?
prefix = kvm-unit-tests PATCH
And maybe even, 'signoff = true'?
Otherwise,
Acked-by: Andrew Jones
Thanks,
drew
100644
> --- a/.gitignore
> +++ b/.gitignore
> @@ -12,6 +12,9 @@ tags
> patches
> .stgit-*
> cscope.*
> +GPATH
> +GRTAGS
> +GTAGS
> *.swp
> /lib/asm
> /lib/config.h
> --
> 2.39.2
>
Acked-by: Andrew Jones
On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/csr.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
>
On Fri, Feb 24, 2023 at 09:16:39PM +1100, Gavin Shan wrote:
> On 2/24/23 8:26 PM, Daniel Henrique Barboza wrote:
> > On 2/24/23 04:09, Gavin Shan wrote:
> > > On 2/24/23 12:18 AM, Daniel Henrique Barboza wrote:
> > > > On 2/23/23 05:13, Gavin Shan wrote:
> > > > > For arm64 and RiscV architecture,
Bin Meng
> Acked-by: Alistair Francis
> Reviewed-by: Andrew Jones
> ---
> MAINTAINERS | 18 --
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9adb628627..7a47c2c724 100644
> --- a/MAINTAINERS
On Thu, Feb 23, 2023 at 04:13:57PM +0800, Gavin Shan wrote:
> For arm64 and RiscV architecture, the driver (/base/arch_topology.c) is
> used to populate the CPU topology in the Linux guest. It's required that
> the CPUs in one socket can't span mutiple NUMA nodes. Otherwise, the Linux
> scheduling
ISCVException write_misa(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> -if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
> +if (!riscv_cpu_cfg(env)->misa_w) {
> /* drop write to misa */
> return RISCV_EXCP_NONE;
> }
> --
> 2.39.2
>
>
Reviewed-by: Andrew Jones
On Tue, Feb 21, 2023 at 03:22:45PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 2/21/23 14:06, Andrew Jones wrote:
> > On Tue, Feb 21, 2023 at 12:49:11PM -0300, Daniel Henrique Barboza wrote:
> > > Hey,
> > >
> > > On 2/16/23 22:42, LIU Zhiwei wrote:
>
> > > Given that allowing the dormant code to write MISA can cause tricky bugs
> > > to solve later on, and we don't have a particularly interesting case of
> > > writing MISA to support today, and we're already not violating the
> > > specification, l
uild_fadt_rev6(tables_blob, tables->linker, s, dsdt);
>
> + acpi_add_table(table_offsets, tables_blob);
> +build_madt(tables_blob, tables->linker, s);
> +
> /* XSDT is pointed to by RSDP */
> xsdt = tables_blob->len;
> build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
Thanks,
drew
(virt_acpi_build_update,
> + build_state, tables.table_data,
> + ACPI_BUILD_TABLE_FILE);
> +assert(build_state->table_mr != NULL);
> +
> +build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
> + build_state,
> + tables.linker->cmd_blob,
> + ACPI_BUILD_LOADER_FILE);
> +
> +build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
> + build_state, tables.rsdp,
> + ACPI_BUILD_RSDP_FILE);
> +
> +qemu_register_reset(virt_acpi_build_reset, build_state);
> +virt_acpi_build_reset(build_state);
> +vmstate_register(NULL, 0, _virt_acpi_build, build_state);
> +
> +/*
> + * Clean up tables but don't free the memory: we track it
> + * in build_state.
> + */
> +acpi_build_tables_cleanup(, false);
> +}
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 379501edcc..e5c474b26e 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -126,4 +126,5 @@ enum {
> 1 + FDT_APLIC_INT_CELLS)
>
> bool virt_is_acpi_enabled(RISCVVirtState *s);
> +void virt_acpi_setup(RISCVVirtState *vms);
> #endif
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
RE_DEBUG
> };
>
> --
> 2.39.1
>
Probably could squash into the previous patch, but anyway
Reviewed-by: Andrew Jones
Thanks,
drew
-------
> 1 file changed, 55 deletions(-)
>
Reviewed-by: Andrew Jones
Thanks,
drew
On Thu, Feb 16, 2023 at 05:33:55PM +0800, Bin Meng wrote:
> On Thu, Feb 16, 2023 at 5:29 PM Andrew Jones wrote:
> >
> > On Wed, Feb 15, 2023 at 03:57:18PM -0300, Daniel Henrique Barboza wrote:
> > > At this moment, and apparently since ever, we have no way of enabling
On Wed, Feb 15, 2023 at 03:57:18PM -0300, Daniel Henrique Barboza wrote:
> At this moment, and apparently since ever, we have no way of enabling
> RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
> the nuts and bolts that handles how to properly write this CSR, has
> always
target/riscv/cpu_helper.c | 6 +++---
> target/riscv/csr.c| 15 ++-
> target/riscv/machine.c| 11 ---
> target/riscv/monitor.c| 2 +-
> target/riscv/op_helper.c | 2 +-
> target/riscv/pmp.c| 8 ++++
> 9 files changed, 34 insertions(+), 66 deletions(-)
>
> --
> 2.39.1
>
>
For the series
Reviewed-by: Andrew Jones
> +RISC-V ACPI Subsystem
> +M: Sunil V L
> +L: qemu-ri...@nongnu.org
> +S: Maintained
> +F: hw/riscv/virt-acpi-build.c
> +
> STM32F100
> M: Alexandre Iooss
> L: qemu-...@nongnu.org
> --
> 2.34.1
>
Please move the ARM ACPI entry down under the main ACPI entry and then
add the RISC-V one there too.
Otherwise,
Reviewed-by: Andrew Jones
gt; bool
> --
> 2.34.1
>
This could probably squashed together with the previous patch.
Reviewed-by: Andrew Jones
led()) {
> riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
> }
> +
> +if (virt_is_acpi_enabled(s)) {
> +virt_acpi_setup(s);
> +}
> }
>
> static void virt_machine_init(MachineState *machine)
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
s('virt-acpi-build.c'))
>
> hw_arch += {'riscv': riscv_ss}
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
+build_append_int_noprefix(table_data, 1, 2); /* number of
> offsets */
s/number/Number/
> +build_append_int_noprefix(table_data, acpi_proc_id, 4); /* UID */
ACPI Processor UID
> +build_append_int_noprefix(table_data, isa_offset, 4);
/* Offsets */
> +acpi_proc_id++;
> +}
> +}
> +
> +acpi_table_end(linker, );
> +}
> +
> /* FADT */
> static void
> build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
> --
> 2.34.1
>
Other than getting the comments to match the spec fields,
Reviewed-by: Andrew Jones
Thanks,
drew
On Mon, Feb 13, 2023 at 08:10:33PM +0530, Sunil V L wrote:
> Add Multiple APIC Description Table (MADT) with the
> INTC structure for each cpu.
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair Francis
> ---
> hw/riscv/virt-acpi-build.c | 37 +
> 1 file
On Mon, Feb 13, 2023 at 08:10:32PM +0530, Sunil V L wrote:
> Add few basic ACPI tables and DSDT with few devices in a
> new file virt-acpi-build.c.
>
> These are mostly leveraged from arm64.
>
> Signed-off-by: Sunil V L
> ---
> hw/riscv/virt-acpi-build.c | 285
irt.h
> @@ -59,6 +59,7 @@ struct RISCVVirtState {
> char *oem_id;
> char *oem_table_id;
> OnOffAuto acpi;
> +const MemMapEntry *memmap;
> };
>
> enum {
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -58,6 +58,7 @@ struct RISCVVirtState {
> int aia_guests;
> char *oem_id;
> char *oem_table_id;
> +OnOffAuto acpi;
> };
>
> enum {
> @@ -123,4 +124,5 @@ enum {
> #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
> 1 + FDT_APLIC_INT_CELLS)
>
> +bool virt_is_acpi_enabled(RISCVVirtState *s);
> #endif
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
t; /* create device tree */
> create_fdt(s, memmap);
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index b3d26135c0..6c7885bf89 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -56,6 +56,8 @@ struct RISCVVirtState {
>
On Tue, Feb 14, 2023 at 09:13:28AM +0530, Sunil V L wrote:
> On Mon, Feb 13, 2023 at 03:48:04PM -0300, Daniel Henrique Barboza wrote:
> > Sunil,
> >
> > This patch is a bit confusing to me. You're using functions that doesn't
> > exist
> > in the code base yet (build_madt and build_rhct) because
On Tue, Feb 07, 2023 at 06:38:15AM -0800, Andrea Bolognani wrote:
> On Tue, Feb 07, 2023 at 03:02:19PM +0100, Thomas Huth wrote:
> > On 07/02/2023 14.56, Andrea Bolognani wrote:
> > > It looks like i440fx and q35 both have an 'acpi' machine property. Is
> > > -no-acpi just sugar for acpi=off?
> >
On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> On 6/2/23 11:54, Andrea Bolognani wrote:
> > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrote:
> > > +object_class_property_add(oc, "acpi", "OnOffAuto",
> > > + virt_get_acpi,
On Tue, Feb 07, 2023 at 09:50:29AM +0100, Philippe Mathieu-Daudé wrote:
> On 6/2/23 13:56, Gerd Hoffmann wrote:
> > On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> > > On 6/2/23 11:54, Andrea Bolognani wrote:
> > > > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L
On Tue, Feb 07, 2023 at 11:57:29AM +0800, Bin Meng wrote:
> On Mon, Feb 6, 2023 at 8:36 PM Andrew Jones wrote:
> >
> > On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> > > On 6/2/23 11:54, Andrea Bolognani wrote:
> > > > On Thu, Feb 02,
On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> On 6/2/23 11:54, Andrea Bolognani wrote:
> > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrote:
> > > +object_class_property_add(oc, "acpi", "OnOffAuto",
> > > + virt_get_acpi,
sr_ops[CSR_TABLE_SIZE];
>
> +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
> +
> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
> void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
>
> void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
>
> +uint8_t satp_mode_max_from_map(uint32_t map);
> +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
> +
> #endif /* RISCV_CPU_H */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6b157806a5..3c02055825 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask =
> MIP_VSSIP;
> static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
> MIP_VSEIP;
> static const target_ulong vsip_writable_mask = MIP_VSSIP;
>
> -static const bool valid_vm_1_10_32[16] = {
> +const bool valid_vm_1_10_32[16] = {
> [VM_1_10_MBARE] = true,
> [VM_1_10_SV32] = true
> };
>
> -static const bool valid_vm_1_10_64[16] = {
> +const bool valid_vm_1_10_64[16] = {
> [VM_1_10_MBARE] = true,
> [VM_1_10_SV39] = true,
> [VM_1_10_SV48] = true,
> @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env,
> int csrno,
>
> static bool validate_vm(CPURISCVState *env, target_ulong vm)
> {
> -if (riscv_cpu_mxl(env) == MXL_RV32) {
> -return valid_vm_1_10_32[vm & 0xf];
> -} else {
> -return valid_vm_1_10_64[vm & 0xf];
> -}
> +RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +
> +return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map));
> }
>
> static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> --
> 2.37.2
>
Other than the minor nit
Reviewed-by: Andrew Jones
Thanks,
drew
On Wed, Jan 25, 2023 at 01:23:45PM +0100, Alexandre Ghiti wrote:
> On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote:
> >
> > On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote:
...
> > > +if (!rv32) {
> > > +for (int i
> }
>
> /* Finally expand the map so that all valid modes are set */
> -for (int i = satp_mode_max - 1; i >= 0; --i) {
> +for (int i = satp_mode_map_max - 1; i >= 0; --i) {
> cpu->cfg.satp_mode.map |= (1 << i);
> }
> }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e37177db5c..b591122099 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -416,13 +416,17 @@ struct RISCVCPUClass {
>
> /*
> * map is a 16-bit bitmap: the most significant set bit in map is the maximum
> - * satp mode that is supported.
> + * satp mode that is supported. It may be chosen by the user and must respect
> + * what qemu implements (valid_1_10_32/64) and what the hw is capable of
> + * (supported bitmap below).
> *
> * init is a 16-bit bitmap used to make sure the user selected a correct
> * configuration as per the specification.
> + *
> + * supported is a 16-bit bitmap used to reflect the hw capabilities.
> */
> typedef struct {
> -uint16_t map, init;
> +uint16_t map, init, supported;
> } RISCVSATPMap;
>
> struct RISCVCPUConfig {
> --
> 2.37.2
>
Reviewed-by: Andrew Jones
Thanks,
drew
On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Tue, Jan 24, 2023 at 11:07:53AM +0100, Alexandre Ghiti wrote:
> On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
> >
> > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > > Currently, the max satp mode is set with the only
On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> Currently, the max satp mode is set with the only constraint that it must be
> implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable
On Mon, Jan 23, 2023 at 12:15:08PM +0100, Alexandre Ghiti wrote:
> On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
> >
> > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > > Currently, the max satp mode is set with the only
On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> Currently, the max satp mode is set with the only constraint that it must be
> implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable
On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
...
> +/* Sets the satp mode to the max supported */
> +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit)
> +{
nit: When passing in the cpu object pointer there's no need to also pass
is_32_bit, we can just use it
On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
> 1 file changed, 10 insertions(+), 9 deletions(-)
Reviewed-by: Andrew Jones
On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
Alexandre Ghiti
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
> ---
> target/riscv/csr.c | 21 +++--
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0db2c233e5..6b157806a5 100644
> ---
On Fri, Jan 20, 2023 at 01:44:41PM +0100, Alexandre Ghiti wrote:
> On Fri, Jan 20, 2023 at 10:53 AM Andrew Jones wrote:
> >
> > On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote:
> > > On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti
> > > w
On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote:
> On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti
> wrote:
> >
> > Hi Alistair, Andrew,
> >
> > On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis
> > wrote:
> > >
> > > On We
On Thu, Jan 19, 2023 at 02:00:27PM +0100, Alexandre Ghiti wrote:
> Hi Alistair, Andrew,
>
> On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis wrote:
> >
> > On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones
> > wrote:
> > >
> > > On Wed, Jan 18, 202
On Wed, Jan 18, 2023 at 05:29:43PM +0100, Alexandre Ghiti wrote:
> Hey Andrew,
>
> On Tue, Jan 17, 2023 at 5:31 PM Andrew Jones wrote:
> >
> > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> > > RISC-V specifies multiple sizes for addre
On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote:
> On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote:
> >
> > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
...
> > > +
> > > +/* Get rid of 32-bit/64-bit incompatibility */
On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
i
> ---
> target/riscv/cpu.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
Reviewed-by: Andrew Jones
On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Fri, Jan 06, 2023 at 08:56:33AM +0100, Alexandre Ghiti wrote:
> On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti
> wrote:
...
> @Andrew: Please let me know when you have some cycles to review this,
I'll try to get to this yet today. Thanks for the ping.
drew
On Tue, Dec 06, 2022 at 06:57:39AM +0100, Alexandre Ghiti wrote:
>
> I can't find the sve* properties you're talking about, can you point them
> to me?
>
target/arm/cpu64.c: cpu_arm_get/set_vq() and arm_cpu_sve_finalize() and
aarch64_add_sve_properties().
Thanks,
drew
On Thu, Dec 01, 2022 at 10:36:23AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Mon, Nov 28, 2022 at 09:10:03PM +, conor.doo...@microchip.com wrote:
> On 28/11/2022 20:41, Atish Kumar Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On Mon, Nov 28, 2022 at 12:38 PM wrote:
> >>
> >> On 28/11/2022
On Fri, Nov 25, 2022 at 11:59:54AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Tue, Nov 08, 2022 at 03:12:42PM +0100, Philippe Mathieu-Daudé wrote:
> On 7/11/22 18:34, Daniel P. Berrangé wrote:
> > On Mon, Nov 07, 2022 at 06:32:01PM +0100, Andrew Jones wrote:
> > > On Mon, Nov 07, 2022 at 04:19:10PM +, Daniel P. Berrangé wrote:
> > > >
On Mon, Nov 07, 2022 at 04:19:10PM +, Daniel P. Berrangé wrote:
> On Mon, Nov 07, 2022 at 03:50:44PM +, Alex Bennée wrote:
> >
> > Sunil V L writes:
> >
> > > On Mon, Nov 07, 2022 at 01:06:38PM +, Peter Maydell wrote:
> > >> On Mon, 7 Nov 2022 at 13:03, Sunil V L wrote:
> > >> >
>
On Mon, Nov 07, 2022 at 11:16:00AM +0530, Sunil V L wrote:
> On Sun, Nov 06, 2022 at 10:20:57PM +0300, Mike Maslenkin wrote:
> > Hello Sunil!
> >
> > What about virt_machine_done() function?
> > kernel_entry variable still points to the second flash started from
> > virt_memmap[VIRT_FLASH].size /
dt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
> qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
> - 2, flashbase, 2, flashsize,
> - 2, flashbase + flashsize, 2, flashsize);
> + 2, flashbase[0], 2, flashsize[0],
> + 2, flashbase[1], 2, flashsize[1]);
> qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
> g_free(name);
> }
> --
> 2.38.0
>
>
Reviewed-by: Andrew Jones
to the guest.
>
> Mayuresh Chitale (3):
> update-linux-headers: Version 6.1-rc2
> target/riscv: Extend isa_ext_data for single letter extensions
> target/riscv: kvm: Support selecting VCPU extensions
>
I already reviewed this internally and it hasn't changed, so
for the series
Revi
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