On Thu, Jun 04, 2020 at 01:55:44PM +0100, Leif Lindholm wrote:
> Hi there,
>
> (all this done on current HEAD: 66234fee9c)
>
> I was looking through the definition of the aarch64 "max" cpu, and
> noticed it invokes aarch64_a57_initfn as a template, followed by
> overriding some feature and ID
On Wed, Jun 03, 2020 at 01:48:10PM +, Salil Mehta wrote:
> (Maybe I should float the ARM VCPU Hotplug patches and let this
> discussion be held over there?)
>
Yes, I think that would be best. Keep in mind that the 'pmu' CPU property
is just one CPU property that we require all CPUs to have,
On Wed, Jun 03, 2020 at 11:45:22AM +, Salil Mehta wrote:
> Hi Andrew,
> Many thanks for the reply.
>
> > From: Andrew Jones [mailto:drjo...@redhat.com]
> > Sent: Wednesday, June 3, 2020 10:38 AM
> > To: Salil Mehta
> > Cc: qemu-devel@nongnu.org; qemu-...@non
On Wed, Jun 03, 2020 at 11:59:23AM +0200, Auger Eric wrote:
> Hi Drew,
>
> On 6/3/20 11:37 AM, Andrew Jones wrote:
> > On Mon, Jun 01, 2020 at 03:04:33PM +, Salil Mehta wrote:
> >> Hello,
> >> I could see below within function fdt_add_pmu_nodes() part of
>
On Mon, Jun 01, 2020 at 03:04:33PM +, Salil Mehta wrote:
> Hello,
> I could see below within function fdt_add_pmu_nodes() part of
> hw/arm/virt.c during virt machine initialization time:
>
> Observation:
> In below function, support of PMU feature is being checked for
> each vcpu and if the
On Tue, Jun 02, 2020 at 03:47:22PM +0800, Ying Fang wrote:
>
>
> On 2020/6/1 20:29, Andrew Jones wrote:
> > On Mon, Jun 01, 2020 at 08:07:31PM +0800, Ying Fang wrote:
> > >
> > >
> > > On 2020/6/1 16:07, Andrew Jones wrote:
> > > > On
On Wed, Jun 03, 2020 at 10:02:08AM +0800, Ying Fang wrote:
> Virtual time adjustment was implemented for virt-5.0 machine type,
> but the cpu property was enabled only for host-passthrough and
> max cpu model. Let's add it for arm cpu which has the gernic
> timer feature enabled.
>
>
>
On Mon, Jun 01, 2020 at 08:07:31PM +0800, Ying Fang wrote:
>
>
> On 2020/6/1 16:07, Andrew Jones wrote:
> > On Sat, May 30, 2020 at 04:56:26PM +0800, Ying Fang wrote:
> > > About the kvm-no-adjvtime CPU property
> > >
> > > Hi Andrew,
> > >
On Sat, May 30, 2020 at 04:56:26PM +0800, Ying Fang wrote:
> About the kvm-no-adjvtime CPU property
>
> Hi Andrew,
> To adjust virutal time, a new kvm cpu property kvm-no-adjvtime
> was introduced to 5.0 virt machine types. However the cpu
> property was enabled only for host-passthrough and max
On Tue, May 05, 2020 at 04:44:17PM +0200, Eric Auger wrote:
> We plan to build the tpm2 table on ARM too. In order to reuse the
> generation code, let's move build_tpm2() to aml-build.c.
>
> No change in the implementation.
>
> Signed-off-by: Eric Auger
> ---
> include/hw/acpi/aml-build.h | 2
On Sat, Apr 25, 2020 at 11:24:14AM +0200, Paolo Bonzini wrote:
> On 24/04/20 14:16, Dr. David Alan Gilbert wrote:
> >>> I was trying to work out whether we need to migrate this state,
> >>> and I'm not sure. Andrew, do you know? I think this comes down
> >>> to "at what points in QEMU's kvm run
On Fri, Apr 17, 2020 at 11:39:25AM +0100, Peter Maydell wrote:
> On Mon, 23 Mar 2020 at 11:32, Beata Michalska
> wrote:
> >
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode info
> > makes it at
pport for this configuration and will remove it in a future version.
> +Running 32-bit guests on a 64-bit Arm host remains supported.
> +
> System emulator devices
> ---
>
> --
> 2.20.1
>
>
Reviewed-by: Andrew Jones
On Mon, Mar 23, 2020 at 11:32:27AM +, Beata Michalska wrote:
> Injecting external data abort through KVM might trigger
> an issue on kernels that do not get updated to include the KVM fix.
> For those and aarch32 guests, the injected abort gets misconfigured
> to be an implementation defined
On Fri, Apr 03, 2020 at 07:07:10AM +0200, Auger Eric wrote:
> Hi Drew,
>
> On 4/2/20 8:01 PM, Andrew Jones wrote:
> > [ Without the fix this test would hang, as timeouts don't work with
> > the migration scripts (yet). Use errata to skip instead of hang. ]
> >
[ Without the fix this test would hang, as timeouts don't work with
the migration scripts (yet). Use errata to skip instead of hang. ]
Signed-off-by: Andrew Jones
---
arm/gic.c | 18 --
errata.txt | 1 +
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arm
On Thu, Apr 02, 2020 at 08:40:42PM +0800, Zenghui Yu wrote:
> Hi Eric,
>
> On 2020/4/2 16:50, Auger Eric wrote:
> > Hi Zenghui,
> >
> > On 3/30/20 12:43 PM, Zenghui Yu wrote:
> > > Hi Eric,
> > >
> > > On 2020/3/20 17:24, Eric Auger wrote:
> > > > Triggers LPIs through the INT command.
> > > >
On Mon, Mar 30, 2020 at 11:56:00AM +0200, Auger Eric wrote:
> Hi,
>
> On 3/30/20 11:11 AM, Andrew Jones wrote:
> > On Mon, Mar 30, 2020 at 10:46:57AM +0200, Auger Eric wrote:
> >> Hi Zenghui,
> >>
> >> On 3/30/20 10:30 AM, Zenghui Yu wrote:
> >
On Wed, Mar 25, 2020 at 10:20:43PM +0100, Auger Eric wrote:
> Hi Zenghui,
>
> On 3/25/20 9:10 AM, Zenghui Yu wrote:
> > Hi Eric,
> >
> > On 2020/3/20 17:24, Eric Auger wrote:
> >> Introduce an helper functions to register
> >> - a new device, characterized by its device id and the
> >> max
On Mon, Mar 30, 2020 at 10:46:57AM +0200, Auger Eric wrote:
> Hi Zenghui,
>
> On 3/30/20 10:30 AM, Zenghui Yu wrote:
> > Hi Eric,
> >
> > On 2020/3/20 17:24, Eric Auger wrote:
> >> +static void its_cmd_queue_init(void)
> >> +{
> >> + unsigned long order = get_order(SZ_64K >> PAGE_SHIFT);
> >>
On Mon, Mar 23, 2020 at 11:32:26AM +, Beata Michalska wrote:
> On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> exception with no valid ISS info to be decoded. The lack of decode info
> makes it at least tricky to emulate those instruction which is one of the
> (many)
On Thu, Mar 12, 2020 at 12:34:01AM +, Beata Michalska wrote:
> On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> exception with no valid ISS info to be decoded. The lack of decode info
> makes it at least tricky to emulate those instruction which is one of the
> (many)
Beata Michalska
> ---
> target/arm/kvm32.c | 15 ++-
> target/arm/kvm64.c | 15 ++-
> 2 files changed, 20 insertions(+), 10 deletions(-)
>
Reviewed-by: Andrew Jones
On Wed, Mar 11, 2020 at 02:51:04PM +0100, Eric Auger wrote:
> This series is a revival of an RFC series sent in Dec 2016 [1].
> Given the amount of code and the lack of traction at that time,
> I haven't respinned until now. However a recent bug found related
> to the ITS migration convinced me
On Wed, Mar 11, 2020 at 02:51:11PM +0100, Eric Auger wrote:
> +/* must be called after gicv3_enable_defaults */
> +void its_enable_defaults(void)
> +{
> + int i;
> +
> + /* Allocate LPI config and pending tables */
> + gicv3_lpi_alloc_tables();
> +
> + for (i = 0; i < nr_cpus; i++)
On Wed, Mar 11, 2020 at 02:51:10PM +0100, Eric Auger wrote:
> Detect the presence of an ITS as part of the GICv3 init
> routine, initialize its base address and read few registers
> the IIDR, the TYPER to store its dimensioning parameters.
> Parse the BASER registers. As part of the init sequence
f we did, then the assumption cpus > GIC_NCPU here wouldn't be correct.
I'd just make this an 'else if (cpus > GIC_NCPU)' to be explicit.
> +error_report("host only supports in-kernel GICv2 emulation "
> + "but more than 8 vcpus are requested");
> +exit(1);
> +}
> break;
> case VIRT_GIC_VERSION_2:
> case VIRT_GIC_VERSION_3:
> --
> 2.20.1
>
Otherwise
Reviewed-by: Andrew Jones
upport in-kernel GICv3 emulation");
> +exit(1);
> +}
> + return;
> +}
> +
> +/* TCG mode */
> +switch (vms->gic_version) {
> +case VIRT_GIC_VERSION_NOSEL:
> vms->gic_version = VIRT_GIC_VERSION_2;
> +break;
> +case VIRT_GIC_VERSION_MAX:
> +vms->gic_version = VIRT_GIC_VERSION_3;
> +break;
> +case VIRT_GIC_VERSION_HOST:
> +error_report("gic-version=host requires KVM");
> +exit(1);
> +case VIRT_GIC_VERSION_2:
> +case VIRT_GIC_VERSION_3:
> +break;
> }
> }
>
> --
> 2.20.1
>
Other than the nit,
Reviewed-by: Andrew Jones
e() function.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Richard Henderson
> Reviewed-by: Andrew Jones
>
> ---
>
> v2 -> v3:
> - add NOTSEL value at the end of the new enum type
> ---
> include/hw/arm/virt.h | 1 +
> hw/arm/virt.c | 54 +++
On Tue, Mar 10, 2020 at 12:00:19PM +0100, Auger Eric wrote:
> Hi Drew,
> On 3/9/20 11:56 AM, Andrew Jones wrote:
> > On Mon, Mar 09, 2020 at 11:24:10AM +0100, Eric Auger wrote:
> >> ipi_enable() code would be reusable for other interrupts
> >> than IPI. Let's
On Mon, Mar 09, 2020 at 12:57:51PM +0100, Andrew Jones wrote:
> This looks pretty good to me. It just needs some resquashing cleanups.
> Does Andre plan to review? I've only been reviewing with respect to
> the framework, not ITS. If no other reviews are expected, then I'll
> qu
On Mon, Mar 09, 2020 at 11:24:07AM +0100, Eric Auger wrote:
> This series is a revival of an RFC series sent in Dec 2016 [1].
> Given the amount of code and the lack of traction at that time,
> I haven't respinned until now. However a recent bug found related
> to the ITS migration convinced me
On Mon, Mar 09, 2020 at 12:45:34PM +0100, Auger Eric wrote:
> >> - for_each_present_cpu(cpu) {
> >> + for (cpu = 0; cpu < nr_cpus; cpu++) {
> >
> > You don't mention this change in the changelog.
> Hey, you can see the changelog is pretty long already & accurate. But
> you're right I missed
On Mon, Mar 09, 2020 at 11:24:17AM +0100, Eric Auger wrote:
...
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> index 0096de6..956d7b8 100644
> --- a/lib/arm/asm/gic-v3-its.h
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -5,9 +5,8 @@
> *
> * This work is licensed under the terms
On Mon, Mar 09, 2020 at 11:24:14AM +0100, Eric Auger wrote:
> its_enable_defaults() enable LPIs at distributor level
> and ITS level.
>
> gicv3_enable_defaults must be called before.
>
> Signed-off-by: Eric Auger
>
> ---
> v3 -> v4:
> - use GITS_BASER_INDIRECT & GITS_BASER_VALID in
On Mon, Mar 09, 2020 at 11:24:14AM +0100, Eric Auger wrote:
> its_enable_defaults() enable LPIs at distributor level
> and ITS level.
>
> gicv3_enable_defaults must be called before.
>
> Signed-off-by: Eric Auger
>
> ---
> v3 -> v4:
> - use GITS_BASER_INDIRECT & GITS_BASER_VALID in
On Mon, Mar 09, 2020 at 11:24:13AM +0100, Eric Auger wrote:
> Detect the presence of an ITS as part of the GICv3 init
> routine, initialize its base address and read few registers
> the IIDR, the TYPER to store its dimensioning parameters.
> Parse the BASER registers. As part of the init sequence
On Mon, Mar 09, 2020 at 11:24:10AM +0100, Eric Auger wrote:
> ipi_enable() code would be reusable for other interrupts
> than IPI. Let's rename it setup_irq() and pass an interrupt
> handler pointer.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - do not export setup_irq anymore
> ---
On Fri, Mar 06, 2020 at 02:21:37PM +0100, Auger Eric wrote:
> Hi Drew,
>
> On 2/7/20 3:06 PM, Andrew Jones wrote:
> > On Tue, Jan 28, 2020 at 11:34:59AM +0100, Eric Auger wrote:
> >> Add two new migration tests. One testing the migration of
> >> a topolo
On Fri, Mar 06, 2020 at 01:55:09PM +0100, Auger Eric wrote:
> Hi Drew,
>
> On 2/7/20 2:15 PM, Andrew Jones wrote:
> > On Tue, Jan 28, 2020 at 11:34:56AM +0100, Eric Auger wrote:
> >> Triggers LPIs through the INT command.
> >>
> >> the test chec
On Thu, Jan 30, 2020 at 12:25:10PM +0100, Eric Auger wrote:
> Test overflows for MEM_ACCESS and SW_INCR events. Also tests
> overflows with 64-bit events.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v1 -> v2:
> - inline setup_irq() code
> ---
> arm/pmu.c | 137
On Thu, Jan 30, 2020 at 12:25:09PM +0100, Eric Auger wrote:
> From: Andre Przywara
>
> A common theme when accessing per-IRQ parameters in the GIC distributor
> is to set fields of a certain bit width in a range of MMIO registers.
> Examples are the enabled status (one bit per IRQ), the
On Thu, Jan 30, 2020 at 12:25:08PM +0100, Eric Auger wrote:
> Test configurations where we transit from 32b to 64b
> counters and conversely. Also tests configuration where
> chain counters are configured but only one counter is
> enabled.
>
> Signed-off-by: Eric Auger
> ---
> arm/pmu.c
On Thu, Jan 30, 2020 at 12:25:06PM +0100, Eric Auger wrote:
> Adds the following tests:
> - event-counter-config: test event counter configuration
> - basic-event-count:
> - programs counters #0 and #1 to count 2 required events
> (resp. CPU_CYCLES and INST_RETIRED). Counter #0 is preset
>
On Thu, Jan 30, 2020 at 12:25:07PM +0100, Eric Auger wrote:
> Add 2 tests exercising chained counters. The first one uses
> CPU_CYCLES and the second one uses SW_INCR.
>
> Signed-off-by: Eric Auger
> ---
> arm/pmu.c | 128 ++
>
On Thu, Jan 30, 2020 at 12:25:06PM +0100, Eric Auger wrote:
> Adds the following tests:
> - event-counter-config: test event counter configuration
> - basic-event-count:
> - programs counters #0 and #1 to count 2 required events
> (resp. CPU_CYCLES and INST_RETIRED). Counter #0 is preset
>
On Thu, Jan 30, 2020 at 12:25:05PM +0100, Eric Auger wrote:
> If event counters are implemented check the common events
> required by the PMUv3 are implemented.
>
> Some are unconditionally required (SW_INCR, CPU_CYCLES,
> either INST_RETIRED or INST_SPEC). Some others only are
> required if the
On Thu, Jan 30, 2020 at 12:25:04PM +0100, Eric Auger wrote:
> This struct aims at storing information potentially used by
> all tests such as the pmu version, the read-only part of the
> PMCR, the number of implemented event counters, ...
>
> Signed-off-by: Eric Auger
> ---
> arm/pmu.c | 30
On Thu, Jan 30, 2020 at 12:25:03PM +0100, Eric Auger wrote:
> As we intend to introduce more PMU tests, let's add
> a sub-test parameter that will allow to categorize
> them. Existing tests are in the cycle-counter category.
>
> Signed-off-by: Eric Auger
> ---
> arm/pmu.c | 24
ed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - replaced defines by enum VirtGICType
> - use that new type for vms->gic_version
> ---
> hw/arm/virt.c | 30 +++---
> include/hw/arm/virt.h | 11 +--
> 2 files changed, 24 insertions(+), 17 deletions(-)
>
Reviewed-by: Andrew Jones
--
> target/arm/kvm_arm.h | 3 +
> 4 files changed, 110 insertions(+), 39 deletions(-)
>
> --
> 2.20.1
>
>
With Richard's enum suggestions
For the series
Reviewed-by: Andrew Jones
On Sun, Mar 01, 2020 at 11:40:40AM +0100, Eric Auger wrote:
> At the moment if the end-user does not specify the gic-version along
> with KVM acceleration, v2 is set by default. However most of the
> systems now have GICv3 and sometimes they do not support GICv2
> compatibility.
>
> This patch
On Wed, Feb 26, 2020 at 06:05:00PM +0100, Eric Auger wrote:
> At the moment if the end-user does not specify the gic-version along
> with KVM acceleration, v2 is set by default. However most of the
> systems now have GICv3 and sometimes they do not support GICv2
> compatibility. In that case we
On Wed, Feb 26, 2020 at 06:05:00PM +0100, Eric Auger wrote:
> At the moment if the end-user does not specify the gic-version along
> with KVM acceleration, v2 is set by default. However most of the
> systems now have GICv3 and sometimes they do not support GICv2
> compatibility. In that case we
On Wed, Feb 26, 2020 at 08:56:03AM +, Peter Maydell wrote:
> On Wed, 26 Feb 2020 at 08:52, Andrew Jones wrote:
> > Although, many QEMU command line users still won't know what to do
> > without an explicit "Try -machine gic-version=host" hint, so that
>
* Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
> + * ENODEV or ENOTSUP mean "can't create GICv2 with
> KVM_CREATE_DEVICE",
> + * and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
> + */
> error_setg_errno(errp, -ret, "erro
On Thu, Feb 20, 2020 at 02:52:45PM -0500, Cleber Rosa wrote:
> On Thu, Feb 20, 2020 at 01:49:40PM -0300, Wainer dos Santos Moschetta wrote:
> > On 2/19/20 11:06 PM, Cleber Rosa wrote:
> > > +
> > > +def test_virt_tcg(self):
> > > +"""
> > > +:avocado: tags=accel:tcg
> > > +
has managed to catch up with all the missing ticks, the time in
> +#the guest and in the host should match.
> #
> # Since: 2.0
> ##
> --
> 2.24.1
>
>
Reviewed-by: Andrew Jones
On Thu, Feb 13, 2020 at 03:36:26PM +0800, Ying Fang wrote:
> On ARM64 platform, cpu frequency is retrieved via ACPI CPPC.
> A virtual cpufreq device based on ACPI CPPC is created to
> present cpu frequency info to the guest.
>
> The default frequency is set to host cpu nominal frequency,
> which
On Tue, Feb 11, 2020 at 03:42:38PM +, Peter Maydell wrote:
> On Thu, 30 Jan 2020 at 11:25, Eric Auger wrote:
> >
> > This series implements tests exercising the PMUv3 event counters.
> > It tests both the 32-bit and 64-bit versions. Overflow interrupts
> > also are checked. Those tests only
On Tue, Jan 28, 2020 at 11:34:59AM +0100, Eric Auger wrote:
> Add two new migration tests. One testing the migration of
> a topology where collection were unmapped. The second test
> checks the migration of the pending table.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - tests belong
On Tue, Jan 28, 2020 at 11:34:58AM +0100, Eric Auger wrote:
> This test maps LPIs (populates the device table, the collection table,
> interrupt translation tables, configuration table), migrates and make
> sure the translation is correct on the destination.
>
> Signed-off-by: Eric Auger
> ---
>
On Tue, Jan 28, 2020 at 11:34:55AM +0100, Eric Auger wrote:
> Implement main ITS commands. The code is largely inherited from
> the ITS driver.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - do not use report() anymore
> - assert if cmd_write exceeds the queue capacity
>
> v1 -> v2:
On Tue, Jan 28, 2020 at 11:34:56AM +0100, Eric Auger wrote:
> Triggers LPIs through the INT command.
>
> the test checks the LPI hits the right CPU and triggers
> the right LPI intid, ie. the translation is correct.
>
> Updates to the config table also are tested, along with inv
> and invall
On Tue, Jan 28, 2020 at 11:34:54AM +0100, Eric Auger wrote:
> Introduce an helper functions to register
> - a new device, characterized by its device id and the
> max number of event IDs that dimension its ITT (Interrupt
> Translation Table). The function allocates the ITT.
>
> - a new
On Tue, Jan 28, 2020 at 11:34:53AM +0100, Eric Auger wrote:
> its_enable_defaults() is the top init function that allocates the
> command queue and all the requested tables (device, collection,
> lpi config and pending tables), enable LPIs at distributor level
> and ITS level.
>
>
On Fri, Feb 07, 2020 at 01:14:37PM +0100, Andrew Jones wrote:
> On Tue, Jan 28, 2020 at 11:34:52AM +0100, Eric Auger wrote:
> > This helper function controls the signaling of LPIs at
> > redistributor level.
> >
> > Signed-off-by: Eric Auger
> >
> > ---
&
On Tue, Jan 28, 2020 at 11:34:52AM +0100, Eric Auger wrote:
> This helper function controls the signaling of LPIs at
> redistributor level.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - move the helper in lib/arm/gic-v3.c
> - rename the function with gicv3_lpi_ prefix
> -
On Tue, Jan 28, 2020 at 11:34:51AM +0100, Eric Auger wrote:
> Allocate the LPI configuration and per re-distributor pending table.
> Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
> by default in the config table.
>
> Also introduce a helper routine that allows to set the
On Tue, Jan 28, 2020 at 11:34:50AM +0100, Eric Auger wrote:
> Detect the presence of an ITS as part of the GICv3 init
> routine, initialize its base address and read few registers
> the IIDR, the TYPER to store its dimensioning parameters.
> Also parse the BASER registers.
>
> This is our first
(vtime is *not not*
> + adjustment is enabled (vtime is not *not*
> adjusted).
>
> When virtual time adjustment is enabled each
> --
> 2.21.1
>
>
Not-Not-Reviewed-by: Andrew Jones
On Thu, Feb 06, 2020 at 09:48:05PM +, Beata Michalska wrote:
> On Wed, 5 Feb 2020 at 16:57, Andrew Jones wrote:
> >
> > On Wed, Jan 29, 2020 at 08:24:41PM +, Beata Michalska wrote:
> > > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
&
On Thu, Feb 06, 2020 at 09:41:10PM +, Beata Michalska wrote:
> On Tue, 4 Feb 2020 at 10:34, Andrew Jones wrote:
> >
> > On Wed, Jan 29, 2020 at 08:24:40PM +, Beata Michalska wrote:
> > > KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
&
On Thu, Feb 06, 2020 at 11:46:49PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/6/20 1:40 PM, Andrew Jones wrote:
> > On Thu, Feb 06, 2020 at 01:08:53PM +0100, Philippe Mathieu-Daudé wrote:
> > ...
> > > > +/* KVM VCPU properties should be prefixed wi
On Thu, Feb 06, 2020 at 01:08:53PM +0100, Philippe Mathieu-Daudé wrote:
...
> > +/* KVM VCPU properties should be prefixed with "kvm-". */
> > +void kvm_arm_add_vcpu_properties(Object *obj)
> > +{
> > +if (!kvm_enabled()) {
>
> This can't happen, right? Can we turn that into an assertion, or
On Wed, Jan 29, 2020 at 08:24:41PM +, Beata Michalska wrote:
> On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> exception with no valid ISS info to be decoded. The lack of decode info
> makes it at least tricky to emulate those instruction which is one of the
> (many)
On Wed, Feb 05, 2020 at 10:19:08AM +, Richard Henderson wrote:
> On 2/4/20 9:45 PM, Alex Bennée wrote:
> >> Also, ZCR_EL1 it itself not correct if the
> >> hardware does not support all vector sizes.
> >>
> >> See some of Andrew Jones' qemu
On Wed, Jan 29, 2020 at 08:24:40PM +, Beata Michalska wrote:
> KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
> As such this should be the last step of sync to avoid potential overwriting
> of whatever changes KVM might have done.
>
> Signed-off-by: Beata Michalska
amp;
> +!strncmp(model->name, cpu_type, len)) {
Four spaces of indent too many on the line above.
> +/* KVM is enabled and we're using this type, so it works. */
> +supported = true;
> + }
> }
>
On Tue, Jan 28, 2020 at 02:53:25PM +0100, Auger Eric wrote:
> Hi,
>
> On 1/28/20 1:41 PM, Andrew Jones wrote:
> > On Tue, Jan 28, 2020 at 01:34:06PM +0100, Auger Eric wrote:
> >> Hi Drew,
> >>
> >> On 1/28/20 1:29 PM, Andrew Jones wrote:
> >&g
On Tue, Jan 28, 2020 at 01:34:06PM +0100, Auger Eric wrote:
> Hi Drew,
>
> On 1/28/20 1:29 PM, Andrew Jones wrote:
> > On Tue, Jan 28, 2020 at 10:52:50AM +, Peter Maydell wrote:
> >> On Tue, 28 Jan 2020 at 10:47, Auger Eric wrote:
> >>> When arm vir
On Tue, Jan 28, 2020 at 10:52:50AM +, Peter Maydell wrote:
> On Tue, 28 Jan 2020 at 10:47, Auger Eric wrote:
> > When arm virt machine is run in accelerated mode with "-cpu host
> > -machine virt", the default gic version is 2.
> >
> > I understand the rationale with TCG where we don't have
On Mon, Jan 27, 2020 at 11:47:35AM -0500, Robert Foley wrote:
> On Mon, 27 Jan 2020 at 10:01, Alex Bennée wrote:
> > > vm-boot-ssh-%: $(IMAGES_DIR)/%.img
> > > $(call quiet-command, \
> > > - $(SRC_PATH)/tests/vm/$* \
> > > + $(PYTHON) $(SRC_PATH)/tests/vm/$* \
> >
On Thu, Jan 23, 2020 at 07:47:19PM -0200, Wainer dos Santos Moschetta wrote:
>
> On 1/22/20 7:02 AM, Andrew Jones wrote:
> > On Tue, Jan 21, 2020 at 10:27:51PM -0300, Wainer dos Santos Moschetta wrote:
> > > +def test_aarch64_virt_kvm(self):
> > > +&qu
On Thu, Jan 23, 2020 at 02:53:42PM +, Peter Maydell wrote:
> On Mon, 20 Jan 2020 at 10:18, Andrew Jones wrote:
> >
> > When dumping a guest with dump-guest-memory also dump the SVE
> > registers if they are in use.
> >
> > Signed-off-by: Andrew Jones
&
On Thu, Jan 23, 2020 at 02:39:48PM +0100, Igor Mammedov wrote:
> On Thu, 23 Jan 2020 13:59:09 +0100
> Andrew Jones wrote:
>
> > On Thu, Jan 23, 2020 at 12:37:45PM +0100, Igor Mammedov wrote:
> > > memory_region_allocate_system_memory() API is going away, so
> > >
---
> v2:
> * fix format string causing build failure on 32-bit host
> (Philippe Mathieu-Daudé )
> v4:
> * move default_ram_size to mps2tz_class_init()
> (Andrew Jones )
>
> CC: drjo...@redhat.com
> CC: peter.mayd...@linaro.org
> CC: qemu-...@nongnu.org
>
rtions(+), 5 deletions(-)
>
I don't know anything about omap_sx1, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
---
> 1 file changed, 19 insertions(+), 13 deletions(-)
>
I don't know anything about nseries, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
letions(-)
I don't know anything about mps2, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
ter.mayd...@linaro.org
> CC: qemu-...@nongnu.org
> ---
> hw/arm/mcimx6ul-evk.c | 25 +
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
I don't know anything about mcimx6ul-evk, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
On Thu, Jan 23, 2020 at 12:37:38PM +0100, Igor Mammedov wrote:
> If user provided non-sense RAM size, board will complain and
> continue running with max RAM size supported.
> Also RAM is going to be allocated by generic code, so it won't be
> possible for board to fix things up for user.
>
>
v...@gmail.com
> CC: peter.mayd...@linaro.org
> CC: qemu-...@nongnu.org
> ---
> hw/arm/cubieboard.c | 25 -
> 1 file changed, 8 insertions(+), 17 deletions(-)
>
I don't know anything about cubieboard, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
> CC: antonynpav...@gmail.com
> CC: peter.mayd...@linaro.org
> CC: qemu-...@nongnu.org
> ---
> hw/arm/digic_boards.c | 40 +---
> 1 file changed, 21 insertions(+), 19 deletions(-)
>
I don't know anything about digic_boards, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
ut I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
: qemu-...@nongnu.org
> CC: j...@tribudubois.net
> ---
> hw/arm/sabrelite.c | 23 ---
> 1 file changed, 8 insertions(+), 15 deletions(-)
>
I don't know anything about sabrelite, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
le changed, 13 insertions(+), 5 deletions(-)
>
I don't know anything about musicpal, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
uma_mem_supported = true;
> mc->auto_enable_numa_with_memhp = true;
> +mc->default_ram_id = "mach-virt.ram";
> }
>
> static void virt_instance_init(Object *obj)
> --
> 2.7.4
>
Reviewed-by: Andrew Jones
le changed, 14 insertions(+), 6 deletions(-)
>
I don't know anything about palm, but I promised Igor to put
another pair of eyes on his changes. Looks fine to me.
Reviewed-by: Andrew Jones
On Thu, Jan 23, 2020 at 12:37:45PM +0100, Igor Mammedov wrote:
> memory_region_allocate_system_memory() API is going away, so
> replace it with memdev allocated MemoryRegion. The later is
> initialized by generic code, so board only needs to opt in
> to memdev scheme by providing
>
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