Re: [PATCH] target/riscv: fix priv enum

On Thu, May 26, 2022 at 2:15 PM Nikita Shubin wrote: > > From: Nikita Shubin > > Add PRIV_VERSION_UNKNOWN to enum, otherwise PRIV_VERSION_1_10_0 will > be overwritten to PRIV_VERSION_1_12_0 in riscv_cpu_realize. > > Fixes: a46d410c5c ("target/riscv: Define simpler privileged spec version >

[PATCH v3 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Patel

[PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 210 +- target/riscv

[PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match

rings to the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 56 +- 1 file changed, 51 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b086eb25da..e6e878ceb3 100644 --- a/target/riscv/cpu.c ++

[PATCH v3 0/4] QEMU RISC-V nested virtualization fixes

s for easy review - Re-worked PATCH7 to force disable extensions if required priv spec version is not staisfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (4): target/riscv: Don't force update priv spec version to latest target/riscv: Add dummy mcou

[PATCH v3 1/4] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by

Re: [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Tue, May 24, 2022 at 3:08 AM Alistair Francis wrote: > > On Thu, May 12, 2022 at 12:47 AM Anup Patel wrote: > > > > We should write transformed instruction encoding of the trapped > > instruction in [m|h]tinst CSR at time of taking trap as defined > > by the R

Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match

On Tue, May 24, 2022 at 3:22 AM Alistair Francis wrote: > > On Fri, May 20, 2022 at 1:07 AM Anup Patel wrote: > > > > On Tue, May 17, 2022 at 5:46 AM Alistair Francis > > wrote: > > > > > > On Thu, May 12, 2022 at 12:52 AM Anup Patel > > >

Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match

On Tue, May 17, 2022 at 5:46 AM Alistair Francis wrote: > > On Thu, May 12, 2022 at 12:52 AM Anup Patel wrote: > > > > We should disable extensions in riscv_cpu_realize() if minimum required > > priv spec version is not satisfied. This also ensures that machines

Re: [PATCH] hw/riscv: virt: Avoid double FDT platform node

On Fri, May 13, 2022 at 1:34 AM Dylan Reid wrote: > > When starting the virt machine with `-machine virt,aia=aplic-imsic`, > both the imsic and aplic init code will add platform fdt nodes by > calling `platform_bus_add_all_fdt_nodes`. This leads to an error at > startup: > ``` >

Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp

INT mtime MMIO register > writable") > > Signed-off-by: Atish Patra Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > hw/intc/riscv_aclint.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/riscv_aclint.c b/hw/in

Re: [PATCH v3 1/3] hw/intc: Move mtimer/mtimecmp to aclint

This also emulates the real hardware > more closely. > > Signed-off-by: Atish Patra Otherwise, this looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > hw/intc/riscv_aclint.c | 41 -- > hw/timer/ibex_timer.c | 1

Re: [PATCH v3 3/3] target/riscv: Add vstimecmp support

On Tue, May 10, 2022 at 3:03 AM Atish Patra wrote: > > vstimecmp CSR allows the guest OS or to program the next guest timer > interrupt directly. Thus, hypervisor no longer need to inject the > timer interrupt to the guest if vstimecmp is used. This was ratified > as a part of the Sstc extension.

Re: [PATCH v3 2/3] target/riscv: Add stimecmp support

On Tue, May 10, 2022 at 3:03 AM Atish Patra wrote: > > stimecmp allows the supervisor mode to update stimecmp CSR directly > to program the next timer interrupt. This CSR is part of the Sstc > extension which was ratified recently. > > Signed-off-by: Atish Patra > --- > target/riscv/cpu.c

[PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Patel

[PATCH v2 8/8] hw/riscv: virt: Fix interrupt parent for dynamic platform devices

: Add support for generating platform FDT entries") Signed-off-by: Anup Patel --- hw/riscv/virt.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3326f4db96..c576173815 100644 --- a/hw/riscv/virt.c +++ b/hw/ri

[PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match

rings to the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f3b61dfd63..25a4ba3e22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -541

[PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by

[PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps

(such as mstatus.TVM or hstatus.VTVM). We improve setting of [m|s]tval CSRs for all types of illegal and virtual instruction traps. Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 2 ++ target/riscv/cpu.h| 8 +++- target/riscv

[PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode

g GVA") Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1aa4f2097..b16bfe0182 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1367

[PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 168 +- target/riscv

[PATCH v2 0/8] QEMU RISC-V nested virtualization fixes

n this series for easy review - Re-worked PATCH7 to force disable extensions if required priv spec version is not staisfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (8): target/riscv: Fix csr number based privilege checking target/riscv: Fix

[PATCH v2 1/8] target/riscv: Fix csr number based privilege checking

When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, the riscv_csrrw_check() function should generate virtual instruction trap instead illegal instruction trap. Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode") Signed-off-by: Anup Patel Reviewed-by

Re: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode

On Mon, May 9, 2022 at 2:54 PM Alistair Francis wrote: > > On Thu, May 5, 2022 at 12:36 PM Anup Patel wrote: > > > > On Thu, May 5, 2022 at 3:21 PM Alistair Francis > > wrote: > > > > > > On Fri, Apr 29, 2022 at 1:38 PM Anup Patel > > >

Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V

On Thu, May 5, 2022 at 4:24 PM Daniel P. Berrangé wrote: > > On Thu, May 05, 2022 at 07:36:51PM +1000, Alistair Francis wrote: > > On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote: > > > > > > On Tue, Apr 19, 2022 at 5:26 PM Atish Patra wrote: > > > > > > > > On Tue, Apr 19, 2022 at 9:51 AM

Re: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode

On Thu, May 5, 2022 at 3:21 PM Alistair Francis wrote: > > On Fri, Apr 29, 2022 at 1:38 PM Anup Patel wrote: > > > > Currently, QEMU does not set hstatus.GVA bit for traps taken from > > HS-mode into HS-mode which breaks the Xvisor nested MMU test suite > > on QEM

Re: [PATCH 3/3] target/riscv: Consider priv spec version when generating ISA string

n for all extensions. >> >> Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the >> device tree") >> Signed-off-by: Anup Patel >> --- >> target/riscv/cpu.c | 36 +++- >> 1 file changed, 19 insertions(

[PATCH 2/3] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Patel -

[PATCH 3/3] target/riscv: Consider priv spec version when generating ISA string

tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 36 +++- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 02ee7d45d8..d8c88b96bc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -

[PATCH 1/3] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel --- target

[PATCH 0/3] QEMU RISC-V priv spec version fixes

This series covers few fixes discovered while trying to detect priv spec version on QEMU virt machine and QEMU sifive_u machine. These patches can also be found in riscv_priv_version_fixes_v1 branch at: https://github.com/avpatel/qemu.git Anup Patel (3): target/riscv: Don't force update priv

[PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode

g GVA") Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1aa4f2097..d83579accf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1434,7 +1434

[PATCH 4/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 168 +- target/riscv

[PATCH 3/4] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps

(such as mstatus.TVM or hstatus.VTVM). We improve setting of [m|s]tval CSRs for all types of illegal and virtual instruction traps. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 2 ++ target/riscv/cpu.h| 8 +++- target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 17

[PATCH 1/4] target/riscv: Fix csr number based privilege checking

When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, the riscv_csrrw_check() function should generate virtual instruction trap instead illegal instruction trap. Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for CSR access") Signed-off-by: Anup Patel --- ta

[PATCH 0/4] QEMU RISC-V nested virtualization fixes

://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hypervisor support to run another hypervisor as Guest/VM. Anup Patel (4): target/riscv: Fix csr number based privilege checking target/riscv: Fix hstatus.GVA bit setting

Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis wrote: > > On Fri, Apr 15, 2022 at 7:37 PM wrote: > > > > From: Frank Chang > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > -cpu command line option. > > > > Signed-off-by: Frank Chang > > Reviewed-by: Jim Shu > >

Re: [PATCH v3] hw/riscv: virt: Exit if the user provided -bios in combination with KVM

user. > > Signed-off-by: Ralf Ramsauer Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > hw/riscv/virt.c | 14 ++ > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index da50cbed43..0960

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

On Wed, Feb 16, 2022 at 9:18 PM Christoph Muellner wrote: > > The RISC-V base cache management operation ISA extension has been > ratified. This patch adds support for the defined instructions. > > The cmo.prefetch instructions are nops for QEMU (no emulation of the memory > hierarchy, no illegal

Re: [EXT] Re: QEMU+KVM on RISC-V + Hypervisor Extension

On Tue, Mar 15, 2022 at 5:47 PM Ralf Ramsauer wrote: > > > > On 15/03/2022 09:33, Anup Patel wrote: > > On Tue, Mar 15, 2022 at 12:18 PM Alistair Francis > > wrote: > >> > >> On Sun, Mar 13, 2022 at 12:12 PM Ralf Ramsauer > >> wrote: > >

Re: QEMU+KVM on RISC-V + Hypervisor Extension

On Tue, Mar 15, 2022 at 12:18 PM Alistair Francis wrote: > > On Sun, Mar 13, 2022 at 12:12 PM Ralf Ramsauer > wrote: > > > > Hi, > > > > I'm trying to run Linux/QEMU+KVM inside an emulated > > qemu-system-riscv64 VM (x86 host). On latest QEMU (1416688c53), > > I run Linux inside QEMU. On host

Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

On Sun, Mar 6, 2022 at 11:06 AM Frank Chang wrote: > > On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra wrote: >> >> >> >> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote: >>> >>> Hi, >>> >>> Am Donnerstag, 3. März 2022, 19:58:38 CET schrieb Atish Patra: >>> > On Fri, Feb 25, 2022 at 11:46

Re: [RFC PATCH 1/3] target/riscv: Rename timer & timecmp to mtimer and mtimecmp

On Fri, Mar 4, 2022 at 8:50 AM Atish Patra wrote: > > Currently, the aclint and ibex timer devices uses the "timer" & > "timecmp" to generate the m-mode timer interrupt. In future, > we will have timer interrupt injected to S/VS mode directly. > No functionality change introduced in this patch.

Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

Heiko Stubner > Signed-off-by: Atish Patra Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > Changes from v2->v3: > 1. Used g_strconcat to replace snprintf & a max isa string length as > suggested by Anup. > 2. I have not included the Tested-by Tag from

[PATCH v10 5/5] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off

[PATCH v10 4/5] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- docs/system

[PATCH v10 2/5] hw/intc: Add RISC-V AIA IMSIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level

[PATCH v10 1/5] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signe

[PATCH v10 3/5] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward

[PATCH v10 0/5] QEMU RISC-V AIA support

From: Anup Patel The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia

Re: [PULL 00/40] riscv-to-apply queue

ror: format '%lx' expects argument of > > type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long > > long unsigned int'} [-Werror=format=] > > > > Printing hwaddrs needs the HWADDR_PRIx macro. (%l and %ll are > > usually the wrong thing in QEMU code a

Re: [PATCH v2] target/riscv: Add isa extenstion strings to the device tree

On Wed, Feb 16, 2022 at 5:39 AM Atish Patra wrote: > > The Linux kernel parses the ISA extensions from "riscv,isa" DT > property. It used to parse only the single letter base extensions > until now. A generic ISA extension parsing framework was proposed[1] > recently that can parse multi-letter

Re: [PATCH v9 00/23] QEMU RISC-V AIA support

On Thu, Feb 10, 2022 at 1:58 PM Atish Patra wrote: > > On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis wrote: > > > > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis > > wrote: > > > > > > On Sat, Feb 5, 2022 at 3:47 AM Anup Pate

Re: [PATCH v9 00/23] QEMU RISC-V AIA support

On Tue, Feb 8, 2022 at 12:27 PM Alistair Francis wrote: > > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis wrote: > > > > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote: > > > > > > From: Anup Patel > > > > > > The advanced i

[PATCH v9 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off

[PATCH v9 22/23] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- docs/system

[PATCH v9 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward

[PATCH v9 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang --- target/riscv/csr.c | 156

[PATCH v9 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled

[PATCH v9 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v9 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

[PATCH v9 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added

[PATCH v9 03/23] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v9 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank

[PATCH v9 07/23] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 119

[PATCH v9 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3

[PATCH v9 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank

[PATCH v9 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Review

[PATCH v9 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level

[PATCH v9 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signe

[PATCH v9 12/23] target/riscv: Implement AIA interrupt filtering CSRs

From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local

[PATCH v9 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv

[PATCH v9 15/23] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang

[PATCH v9 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example

[PATCH v9 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

From: Anup Patel The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.h| 14 +- target

[PATCH v9 04/23] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish

[PATCH v9 06/23] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed

[PATCH v9 00/23] QEMU RISC-V AIA support

From: Anup Patel The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia

Re: [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

On Fri, Jan 28, 2022 at 7:24 AM Alistair Francis wrote: > > On Thu, Jan 20, 2022 at 1:55 AM Anup Patel wrote: > > > > From: Anup Patel > > > > The RISC-V AIA (Advanced Interrupt Architecture) defines a new > > interrupt controller for MSIs (message signal in

Re: [PATCH v8 00/23] QEMU RISC-V AIA support

Hi Alistair, On Wed, Jan 19, 2022 at 8:56 PM Anup Patel wrote: > > From: Anup Patel > > The advanced interrupt architecture (AIA) extends the per-HART local > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > and Advanced PLIC (wired interrupt controlle

[PATCH v3 0/3] Improve RISC-V spike machine bios support

/qemu.git Changes since v2: - Remove ELF file names from .gitlab-ci.d/opensbi.yml in PATCH3 Changes since v1: - Use htif_uses_elf_symbols() in htif_mm_init() for PATCH1 - Added PATCH2 and PATCH3 to remove ELF bios images Anup Patel (3): hw/riscv: spike: Allow using binary firmware as bios hw

Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

On Thu, Jan 20, 2022 at 1:49 PM Frank Chang wrote: > > On Thu, Jan 20, 2022 at 12:20 AM Anup Patel wrote: >> >> Hi Frank, >> >> On Wed, Jan 19, 2022 at 9:07 PM Frank Chang wrote: >> > >> > On Wed, Jan 19, 2022 at 11:27 PM Anup Patel wrote: >

[PATCH v3 2/3] hw/riscv: Remove macros for ELF BIOS image names

Now that RISC-V Spike machine can use BIN BIOS images, we remove the macros used for ELF BIOS image names. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c| 4 ++-- include/hw/riscv/boot.h | 2 -- 2 files changed, 2 insertions(+), 4

[PATCH v3 1/3] hw/riscv: spike: Allow using binary firmware as bios

machine can now use OpenSBI firmware BIN as bios. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/char/riscv_htif.c | 33 +++-- hw/riscv/spike.c | 41 ++-- include/hw/char/riscv_htif.h

Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images

On Wed, Jan 19, 2022 at 12:26 PM Bin Meng wrote: > > On Tue, Jan 18, 2022 at 7:18 PM Anup Patel wrote: > > > > Now that all RISC-V machines can use OpenSBI BIN images, we remove > > OpenSBI ELF images and also exclude these images from BIOS build. > >

[PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off

[PATCH v8 22/23] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- docs/system

[PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

[PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signe

[PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang

[PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank

Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

Hi Frank, On Wed, Jan 19, 2022 at 9:07 PM Frank Chang wrote: > > On Wed, Jan 19, 2022 at 11:27 PM Anup Patel wrote: >> >> From: Anup Patel >> >> The RISC-V AIA (Advanced Interrupt Architecture) defines a new >> interrupt controller for wired interrupts call

[PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv

[PATCH v8 07/23] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 119

[PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example

[PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward

[PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3

[PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added

[PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled

[PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Review

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