int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
+
+ret = apic_msr_write(index, data);
+if (ret < 0) {
+raise_exception(env, EXCP0D_GPF, 0);
+}
+
+break;
+}
case MSR_FSBASE:
wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
break;
Acked-by: Bui Quang Minh
ommonState *s)
Reviewed-by: Bui Quang Minh
Thanks,
Quang Minh.
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins
Acked-by: Peter Xu
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions
00 00 //
+0080: D3 29 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .)..
+0090: 02 00 00 00 02 08 00 00 02 10 00 00 02 F8 00 00 //
+00A0: 02 FA 00 00 02 FB 00 00 48 00 00 00 00 A0 00 01 // ....H...
Signed-off-by: Bui Quang
Following the instructions in bios-tables-test, this lists that IVRS.ivrs
in ACPI table will be changed to add new IVHD type 0x11.
Signed-off-by: Bui Quang Minh
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test
This commit creates apic_register_read/write which are used by both
apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access.
The apic_msr_read/write returns -1 on error, accelerator can use this to
raise the appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/intc
,
accelerator can use this to raise appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/i386/kvm/apic.c | 3 +-
hw/i386/xen/xen_apic.c | 3 +-
hw/intc/apic.c | 62 +++-
hw/intc/apic_common.c| 13
nded_log_dest to store APIC_LDR information in x2APIC
instead of extending log_dest for backward compatibility in vmstate
Version 2 changes,
- Add support for APIC ID larger than 255
- Adjust AMD iommu for x2APIC support
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
in amd_iommu.c.
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 129 ---
hw/i386/amd_iommu-stub.c | 26
hw/i386/amd_iommu.c | 29 -
hw/i386/amd_iommu.h | 16 +++--
hw/i386/meson.build | 3 +-
5 files changed, 145
register access are supported.
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 6 +-
hw/intc/apic.c | 289
hw/intc/apic_common.c | 9 +
include/hw/i386/apic.h | 3 +-
include/hw/i386/apic_internal.h | 7
On 1/8/24 18:03, Thomas Huth wrote:
On 05/01/2024 20.11, Peter Maydell wrote:
https://gitlab.com/qemu-project/qemu/-/jobs/5871592479
failed with
$ htags -anT --tree-view=filetree -m qemu_init -t "Welcome to the QEMU
sourcecode"
htags: Negative exec line limit = -371
Does anybody have any
On 12/28/23 22:44, Bui Quang Minh wrote:
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted
00 00 //
+0080: D3 29 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .)..
+0090: 02 00 00 00 02 08 00 00 02 10 00 00 02 F8 00 00 //
+00A0: 02 FA 00 00 02 FB 00 00 48 00 00 00 00 A0 00 01 // ....H...
Signed-off-by: Bui Quang
This commit creates apic_register_read/write which are used by both
apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access.
The apic_msr_read/write returns -1 on error, accelerator can use this to
raise the appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/intc
,
accelerator can use this to raise appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/i386/kvm/apic.c | 3 +-
hw/i386/xen/xen_apic.c | 3 +-
hw/intc/apic.c | 62 +++-
hw/intc/apic_common.c| 13
Following the instructions in bios-tables-test, this lists that IVRS.ivrs
in ACPI table will be changed to add new IVHD type 0x11.
Signed-off-by: Bui Quang Minh
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test
device.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 129 +++
hw/i386/amd_iommu.c | 29 +-
hw/i386/amd_iommu.h | 16 --
3 files changed, 117 insertions(+), 57 deletions(-)
diff --git a/hw/i386/acpi
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins
Acked-by: Peter Xu
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions
nformation in x2APIC
instead of extending log_dest for backward compatibility in vmstate
Version 2 changes,
- Add support for APIC ID larger than 255
- Adjust AMD iommu for x2APIC support
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (7):
i386
register access are supported.
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 6 +-
hw/intc/apic.c | 289
hw/intc/apic_common.c | 9 +
include/hw/i386/apic.h | 3 +-
include/hw/i386/apic_internal.h | 7
Following the instructions in bios-tables-test, this lists that IVRS.ivrs
in ACPI table will be changed to add new IVHD type 0x11.
Signed-off-by: Bui Quang Minh
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test
device.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 129 +++
hw/i386/amd_iommu.c | 29 +-
hw/i386/amd_iommu.h | 16 --
3 files changed, 117 insertions(+), 57 deletions(-)
diff --git a/hw/i386/acpi
,
accelerator can use this to raise appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/i386/kvm/apic.c | 3 +-
hw/i386/xen/xen_apic.c | 3 +-
hw/intc/apic.c | 62 +++-
hw/intc/apic_common.c| 13
00 00 //
+0080: D3 29 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .)..
+0090: 02 00 00 00 02 08 00 00 02 10 00 00 02 F8 00 00 //
+00A0: 02 FA 00 00 02 FB 00 00 48 00 00 00 00 A0 00 01 // ....H...
Signed-off-by: Bui Quang
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins
Acked-by: Peter Xu
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions
register access are supported.
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 6 +-
hw/intc/apic.c | 289
hw/intc/apic_common.c | 9 +
include/hw/i386/apic.h | 3 +-
include/hw/i386/apic_internal.h | 7
This commit creates apic_register_read/write which are used by both
apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access.
The apic_msr_read/write returns -1 on error, accelerator can use this to
raise the appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/intc
t AMD iommu for x2APIC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (7):
i386/tcg: implement x2APIC registers MSR access
apic: add support for x2APIC mode
apic, i386/tcg: add x2apic transitions
intel_iommu: allow Extended Interrupt
On 11/9/23 21:32, Joao Martins wrote:
On 09/11/2023 14:10, Bui Quang Minh wrote:
On 11/9/23 17:11, Santosh Shukla wrote:
On 10/24/2023 8:51 PM, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers
On 11/9/23 02:44, Michael S. Tsirkin wrote:
On Wed, Nov 08, 2023 at 09:22:18PM +0700, Bui Quang Minh wrote:
On 11/7/23 07:39, Michael S. Tsirkin wrote:
On Tue, Oct 24, 2023 at 10:21:05PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
On 11/9/23 17:11, Santosh Shukla wrote:
On 10/24/2023 8:51 PM, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to support x2APIC interrupt
On 11/7/23 07:39, Michael S. Tsirkin wrote:
On Tue, Oct 24, 2023 at 10:21:05PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used
at 18:08, Bui Quang Minh wrote:
@@ -455,6 +469,19 @@ void helper_rdmsr(CPUX86State *env)
val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16);
break;
}
+case MSR_APIC_START ... MSR_APIC_END: {
+int index = (uint32_t)env->regs[R_ECX
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins
Acked-by: Peter Xu
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions
device.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 129 +++
hw/i386/amd_iommu.c | 29 +-
hw/i386/amd_iommu.h | 16 --
3 files changed, 117 insertions(+), 57 deletions(-)
diff --git a/hw/i386/acpi
This commit creates apic_register_read/write which are used by both
apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access.
The apic_msr_read/write returns -1 on error, accelerator can use this to
raise the appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/intc
,
accelerator can use this to raise appropriate exception.
Signed-off-by: Bui Quang Minh
---
hw/i386/kvm/apic.c | 3 +-
hw/i386/xen/xen_apic.c | 3 +-
hw/intc/apic.c | 62 +++-
hw/intc/apic_common.c| 13
register access are supported.
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 6 +-
hw/intc/apic.c | 280
hw/intc/apic_common.c | 9 +
include/hw/i386/apic.h | 3 +-
include/hw/i386/apic_internal.h | 7
rt for APIC ID larger than 255
- Adjust AMD iommu for x2APIC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (5):
i386/tcg: implement x2APIC registers MSR access
apic: add support for x2APIC mode
apic, i386/tcg: add x2apic transitions
@system -
fee0-feef (prio 4096, i/o): apic-msi
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 24 ++--
hw/intc/ioapic.c | 32 +++-
hw/pci/pci.c
On 9/26/23 23:06, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to support x2APIC interrupt remapping. With this
series, we can now boot
On 10/4/23 13:51, Michael S. Tsirkin wrote:
On Tue, Sep 26, 2023 at 11:23:53PM +0700, Bui Quang Minh wrote:
On 9/26/23 23:06, Bui Quang Minh wrote:
Version 8 changes,
- Patch 2, 4:
+ Rebase to master and resolve conflicts in these 2 patches
The conflicts when rebasing is due
On 9/26/23 23:06, Bui Quang Minh wrote:
Version 8 changes,
- Patch 2, 4:
+ Rebase to master and resolve conflicts in these 2 patches
The conflicts when rebasing is due to the commit 9926cf34de5fa15da
("target/i386: Allow elision of kvm_enable_x2apic()"). AFAIK, this
c
device.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 129 +++
hw/i386/amd_iommu.c | 29 +-
hw/i386/amd_iommu.h | 16 --
3 files changed, 117 insertions(+), 57 deletions(-)
diff --git a/hw/i386/acpi
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins
Acked-by: Peter Xu
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc
nded_log_dest to store APIC_LDR information in x2APIC
instead of extending log_dest for backward compatibility in vmstate
Version 2 changes,
- Add support for APIC ID larger than 255
- Adjust AMD iommu for x2APIC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
register access are supported.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 6 +-
hw/intc/apic.c | 266
hw/intc/apic_common.c | 9 ++
include/hw/i386/apic.h | 3
ackward compatibility in vmstate
Version 2 changes,
- Add support for APIC ID larger than 255
- Adjust AMD iommu for x2APIC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (5):
i386/tcg: implement x2APIC registers MSR access
apic: add su
register access are supported.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 8 +-
hw/intc/apic.c | 266
hw/intc/apic_common.c | 9 ++
include/hw/i386/apic.h | 3
device.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 129 +++
hw/i386/amd_iommu.c | 29 +-
hw/i386/amd_iommu.h | 16 --
3 files changed, 117 insertions(+), 57 deletions(-)
diff --git a/hw/i386/acpi
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4
On 7/21/23 03:47, Peter Xu wrote:
On Mon, Jul 17, 2023 at 11:29:56PM +0700, Bui Quang Minh wrote:
On 7/17/23 17:47, Joao Martins wrote:
+Peter, +Jason (intel-iommu maintainer/reviewer)
Thanks for copying me, Joan.
On 15/07/2023 16:22, Bui Quang Minh wrote:
As userspace APIC now supports
On 7/17/23 17:47, Joao Martins wrote:
+Peter, +Jason (intel-iommu maintainer/reviewer)
On 15/07/2023 16:22, Bui Quang Minh wrote:
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Reviewed-by: Michael S. Tsirkin
>env);
s->spurious_vec &= ~APIC_SV_ENABLE;
}
+*/
}
Signed-off-by: Bui Quang Minh
---
hw/i386/kvm/apic.c | 2 +-
hw/intc/apic.c | 37 ++---
hw/intc/apic_common.c | 41 +
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/hw/i386
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4
register access are supported.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 8 +-
hw/intc/apic.c | 266
hw/intc/apic_common.c | 9 ++
include/hw/i386/apic.h | 3
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc
device.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 129 +++
hw/i386/amd_iommu.c | 29 +-
hw/i386/amd_iommu.h | 16 --
3 files changed, 117 insertions(+), 57 deletions(-)
diff --git a/hw/i386/acpi
IC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (5):
i386/tcg: implement x2APIC registers MSR access
apic: add support for x2APIC mode
apic, i386/tcg: add x2apic transitions
intel_iommu: allow Extended Interrupt Mode when usin
On 7/15/23 21:28, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to support x2APIC interrupt remapping. With this
series, we can now boot
register access are supported.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 8 +-
hw/intc/apic.c | 266
hw/intc/apic_common.c | 9 ++
include/hw/i386/apic.h | 3
nformation in x2APIC
instead of extending log_dest for backward compatibility in vmstate
Version 2 changes,
- Add support for APIC ID larger than 255
- Adjust AMD iommu for x2APIC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (5):
i386
device.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 127 ++-
hw/i386/amd_iommu.c | 30 +-
hw/i386/amd_iommu.h | 16 --
3 files changed, 117 insertions(+), 56 deletions(-)
diff --git a/hw/i386/acpi
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/hw/i386
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4
On 7/11/23 01:39, Michael S. Tsirkin wrote:
On Mon, May 22, 2023 at 11:31:52PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted
On 7/11/23 01:37, Michael S. Tsirkin wrote:
On Fri, Jun 23, 2023 at 10:28:43PM +0700, Bui Quang Minh wrote:
On 6/23/23 03:26, Michael S. Tsirkin wrote:
On Mon, May 22, 2023 at 11:31:57PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
On 6/23/23 03:26, Michael S. Tsirkin wrote:
On Mon, May 22, 2023 at 11:31:57PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used
On 5/14/23 15:55, Bui Quang Minh wrote:
On 5/12/23 21:39, Michael S. Tsirkin wrote:
On Tue, Apr 11, 2023 at 09:24:40PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether
enable
this feature or not. When XTSup is enabled, additional bytes in IRTE
device.
Signed-off-by: Bui Quang Minh
---
hw/i386/acpi-build.c | 127 ++-
hw/i386/amd_iommu.c | 21 ++-
hw/i386/amd_iommu.h | 16 --
3 files changed, 108 insertions(+), 56 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/hw/i386
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4
register access are supported.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/i386/x86.c | 8 +-
hw/intc/apic.c | 266
hw/intc/apic_common.c | 9 ++
include/hw/i386/apic.h | 3
IC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (5):
i386/tcg: implement x2APIC registers MSR access
apic: add support for x2APIC mode
apic, i386/tcg: add x2apic transitions
intel_iommu: allow Extended Interrupt Mode when using usersp
On 5/15/23 03:44, Michael S. Tsirkin wrote:
On Sun, May 14, 2023 at 03:55:11PM +0700, Bui Quang Minh wrote:
On 5/12/23 21:39, Michael S. Tsirkin wrote:
On Tue, Apr 11, 2023 at 09:24:40PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
On 5/12/23 21:39, Michael S. Tsirkin wrote:
On Tue, Apr 11, 2023 at 09:24:40PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used
On 4/11/23 21:24, Bui Quang Minh wrote:
[Reposting due to broken threading in previous post]
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to support x2APIC
On 4/21/23 14:57, Michael S. Tsirkin wrote:
On Tue, Apr 11, 2023 at 09:24:35PM +0700, Bui Quang Minh wrote:
[Reposting due to broken threading in previous post]
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386
for
feature report to operating system. This is because Linux does not use
XTSup in IOMMU Feature Reporting field of IVHD type 0x10 but only use XTSup
bit in EFR Register Image of IVHD 0x11 to indicate x2APIC support (see
init_iommu_one in linux/drivers/iommu/amd/init.c)
Signed-off-by: Bui Quang Minh
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc/apic_common.c| 7
register access are supported.
Signed-off-by: Bui Quang Minh
---
Version 3 changes:
- Allow APIC ID > 255 only when x2APIC feature is supported on CPU
- Make physical destination mode IPI which has destination id 0x
a broadcast to xAPIC CPUs
- Make cluster address 0xf in cluster mo
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4 +-
include/hw/i386/apic.h
st AMD iommu for x2APIC suuport
- Reorganize and split patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (5):
i386/tcg: implement x2APIC registers MSR access
apic: add support for x2APIC mode
apic, i386/tcg: add x2apic transitions
intel_iommu: allow Extended In
On 4/11/23 14:09, Michael S. Tsirkin wrote:
On Sun, Apr 09, 2023 at 09:40:22PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc/apic_common.c| 7
for
feature report to operating system. This is because Linux does not use
XTSup in IOMMU Feature Reporting field of IVHD type 0x10 but only use XTSup
bit in EFR Register Image of IVHD 0x11 to indicate x2APIC support (see
init_iommu_one in linux/drivers/iommu/amd/init.c)
Signed-off-by: Bui Quang Minh
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4 +-
include/hw/i386/apic.h
register access are supported.
Signed-off-by: Bui Quang Minh
---
Version 3 changes:
- Allow APIC ID > 255 only when x2APIC feature is supported on CPU
- Make physical destination mode IPI which has destination id 0x
a broadcast to xAPIC CPUs
- Make cluster address 0xf in cluster mo
it patch 1,2 into patch 1,2,3 in version 2
Thanks,
Quang Minh.
Bui Quang Minh (5):
i386/tcg: implement x2APIC registers MSR access
apic: add support for x2APIC mode
apic, i386/tcg: add x2apic transitions
intel_iommu: allow Extended Interrupt Mode when using userspace APIC
amd_iommu
1 - 100 of 125 matches
Mail list logo
