From: Corvin Köhne
We have to update the calculation of the stolen memory size because
we've seen devices using values of 0xf0 and above for the graphics mode
select field. The new calculation was taken from the linux kernel [1].
[1]
https://github.com/torvalds/linux/blob/7c626ce4bae1ac14f60076
From: Corvin Köhne
Intel changes it's specification quite often e.g. the location and size
of the BDSM register has change for gen 11 devices and later. This
causes our emulation to fail on those devices. So, it's impossible for
us to use a suitable default value for unknown devices. Instead of
r
hilippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
---
hw/vfio/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index
98bd4dcceadc62517a510b81ad4a2a4d8ae61b22..c475c273fd8de156c68bca3f6eaf804c94276ff6
100644
--- a/hw/vf
From: Corvin Köhne
ElkhartLake and TigerLake devices were tested in legacy mode with Linux
and Windows VMs. Both are working properly. It's likely that other Intel
GPUs of gen 11 and 12 like IceLake device are working too. However,
we're only adding known good devices for now.
Signed-off-by: Cor
From: Corvin Köhne
The stolen memory is required for the GOP (EFI) driver and the Windows
driver. While the GOP driver seems to work with any stolen memory size,
the Windows driver will crash if the size doesn't match the size
allocated by the host BIOS. For that reason, it doesn't make sense to
From: Corvin Köhne
The BDSM register is mirrored into MMIO space at least for gen 11 and
later devices. Unfortunately, the Windows driver reads the register
value from MMIO space instead of PCI config space for those devices [1].
Therefore, we either have to keep a 1:1 mapping for the host and gu
The following changes since commit ea9cdbcf3a0b8d5497cddf87990f1b39d8f3bb0a:
Merge tag 'hw-misc-20240913' of https://github.com/philmd/qemu into staging
(2024-09-15 18:27:40 +0100)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-vfio-20240917
for you to
From: Corvin Köhne
We're soon going to add support for legacy mode to ElkhartLake and
TigerLake devices. Those are gen 11 and 12 devices. At the moment, all
devices identified by our igd_gen function do support legacy mode. This
won't change when adding our new devices of gen 11 and 12. Therefore
Hello Harsh,
On 9/17/24 08:03, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing the arch specific code for the now deprecated machine types.
Suggested-by: Cédric Le Goater
Signed-off-by
On 9/13/24 16:48, Thomas Huth wrote:
The pci-bridge device is not usable on s390x, so introduce a Kconfig
switch that allows to disable it.
Signed-off-by: Thomas Huth
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci-bridge/Kconfig | 5 +
hw/pci-bridge/meson.build | 2
is connected to GICINT130_INTC at bit 0.
I2C bus 15 is connected to GICINT130_INTC at bit 15.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm
From: Jamin Lin
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 ++
1 file changed, 10
AspeedI2CClass and
use it to create either a share pool buffer or bus pool buffers
in aspeed_i2c_realize. Update each pull buffer size to 0x10 for AST2500
and 0x20 for AST2600 and AST1030.
Incrementing the version of aspeed_i2c_bus_vmstate to 6.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
INTC orgate input pin
if users only provide the device id with its bus number index.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
overity happy by doing the shift on
unsigned numbers.
Resolves: Coverity CID 1547742
Signed-off-by: Peter Maydell
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 3
– 0x107F: Device 15
Introduce a new class attribute to make user set each I2C bus gap size.
Update formula to create all I2C bus register memory regions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/i2c/aspeed_i2c.h | 1 +
hw/i2c/aspeed_i2c.c | 3 ++-
2 files
From: Jamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 " which
is 64bits address.
It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)"
and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)"
registers to save the high pa
ion is not increased
because it was done earlier in the same series.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/i2c/aspeed_i2c.h | 9 +--
hw/i2c/aspeed_i2c.c | 51 +++--
2 files changed, 33 insertions(+), 27 deletions(-)
di
From: Jamin Lin
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/i2c/aspeed_i2c.h | 1 +
hw/i2c/aspeed_i2c.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 8e62ec64f835..b42c4dc5844b 100644
--- a/include/hw
dram physical
high part address for DMA operation.
(high part physical address bit[7:0] – 4)
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
in
buffer from the datasheet.
An I2C controller registers owns 8KB address space.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/i2c/aspeed_i2c.h | 1 +
hw/i2c/aspeed_i2c.c | 62 +
2 files changed, 63 insertions(+)
diff --git a
The following changes since commit ea9cdbcf3a0b8d5497cddf87990f1b39d8f3bb0a:
Merge tag 'hw-misc-20240913' of https://github.com/philmd/qemu into staging
(2024-09-15 18:27:40 +0100)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspeed-20240916
for you t
Hello Harsh,
On 2/19/24 09:29, Nicholas Piggin wrote:
From: Cédric Le Goater
pseries machines before version 2.11 have undergone many changes to
correct issues, mostly regarding migration compatibility. This is
obfuscating the code uselessly and makes maintenance more difficult.
Remove them
On 9/16/24 14:41, Mattias Nissler wrote:
Thanks Cédric, I can reproduce now, and my proposed patch fixes avoids
the crash as expected.
disk images for macos9 and macosx10 all boot.
C.
Mattias,
Cédric, can you try with the above patch and/or
crash seems gone.
share more details of your setup so I can verify
You will need a Linnux powerpc or powerpc64 image for mac machines,
which are not common now days, or MacOS images. My debian images
are big. I will try to build you
On 9/16/24 10:23, Mattias Nissler wrote:
Thanks for the report, and my apologies for the breakage.
On Fri, Sep 13, 2024 at 4:47 PM Peter Xu wrote:
On Fri, Sep 13, 2024 at 04:35:32PM +0200, Cédric Le Goater wrote:
Hello,
+Mark (for the Mac devices)
On 9/9/24 22:11, Peter Xu wrote:
From
Hello Saif,
On 3/21/24 11:04, Saif Abrar wrote:
Hello,
This series updates the existing PHB4 model to the latest spec:
"Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00".
Updates include the following:
- implemented sticky reset logic
- implemented read-only, write-on
Hello Michael,
On 9/13/24 18:16, Michael Kowal wrote:
In XIVE Gen 2 there are many operations that were not modeled and are
needed for PowerVM. These changes are associated with the following Thread
Interrupt Management Area subjects:
- OS context
- Thread context
- Pulling contexts to 'c
-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/ppc/xive.h | 2 +-
hw/intc/xive.c| 6 +++---
hw/intc/xive2.c | 20 ++--
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw
Hello,
+Mark (for the Mac devices)
On 9/9/24 22:11, Peter Xu wrote:
From: Mattias Nissler
When DMA memory can't be directly accessed, as is the case when
running the device model in a separate process without shareable DMA
file descriptors, bounce buffering is used.
It is not uncommon for de
Hello,
On 9/13/24 15:24, Chalapathi V wrote:
On 12-09-2024 22:25, Cédric Le Goater wrote:
Chalapthi,
On 8/7/24 22:28, Philippe Mathieu-Daudé wrote:
v2:
- Cover PowerNV SSI in MAINTAINERS
- Use GLib API in pnv_spi_xfer_buffer_free()
- Simplify returning early
Supersedes
ned-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/ppc/xive2.h | 2 ++
include/hw/ppc/xive2_regs.h | 16 +
include/hw/ppc/xive_regs.h | 1 +
hw/intc/xive.c | 9 ++---
hw/intc/xive2.c
_blk(cam);
*nvp_idx = xive2_nvp_idx(cam);
-*vo = !!(cam & TM2_QW1W2_VO);
-*ho = !!(cam & TM2_QW1W2_HO);
+*valid = !!(cam & TM2_QW1W2_VO);
+*hw = !!(cam & TM2_QW1W2_HO);
This change belongs to another patch. Anyhow,
Reviewed-by: Cédric Le Goater
Thanks,
C.
Hello Dan,
On 9/12/24 18:09, dan tan wrote:
From: dan tan
SPI interface to TPM TIS implementation via swtpm
I would split this patch in 3 :
1. device model
2. activation for the PowerNV machines
3. unit tests
Each with a slightly more detailed commit log please. one line
is very minimal fo
Chalapthi,
On 8/7/24 22:28, Philippe Mathieu-Daudé wrote:
v2:
- Cover PowerNV SSI in MAINTAINERS
- Use GLib API in pnv_spi_xfer_buffer_free()
- Simplify returning early
Supersedes: <20240806134829.351703-3-chalapath...@linux.ibm.com>
I was wondering where we were on this series. I see there w
Hello Jim,
On 9/12/24 08:36, Jim Shu wrote:
Hi Cédric,
Thank you very much for the quick response!
I have checked the error API again. It seems to be my porting issue of
set_iommu_device() callback.
Are you adding support for a new IOMMU ?
I think "pci_device_set_iommu_device(..., *errp)"
On 9/12/24 10:09, Avihai Horon wrote:
On 09/09/2024 18:11, Peter Xu wrote:
External email: Use caution opening links or attachments
On Mon, Sep 09, 2024 at 03:52:39PM +0300, Avihai Horon wrote:
On 05/09/2024 21:31, Peter Xu wrote:
External email: Use caution opening links or attachments
O
On 9/12/24 10:26, Avihai Horon wrote:
On 09/09/2024 21:07, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
On 9.09.2024 13:41, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
- return vfio_migration_set_state(vbasedev, VFIO_DEVICE_STATE_RESUMING,
- vbasedev->migration->device_state, errp);
+ migration->load_bufs_thread_finished = false;
+ migration->load_bufs_thread_want_exit = false;
+ qemu_thread_create(&migration->load_bufs_thread, "vfio-load-bufs",
+
On 9/12/24 09:39, Pierrick Bouvier wrote:
This patch is part of a series that moves towards a consistent use of
g_assert_not_reached() rather than an ad hoc mix of different
assertion mechanisms.
Signed-off-by: Pierrick Bouvier
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc
On 9/9/24 23:10, Michael Kowal wrote:
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-o
On 9/9/24 23:10, Michael Kowal wrote:
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified b
Hello Jim,
On 9/12/24 07:17, Jim Shu wrote:
pci_dev_realize() use the local error variable, which requires
`error_setg()` API to allocate the error object at first.
Signed-off-by: Jim Shu
---
hw/vfio/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/pci.c b/h
On 9/9/24 17:10, Guenter Roeck wrote:
On 9/9/24 04:20, Joel Stanley wrote:
On Sat, 31 Aug 2024 at 05:41, Guenter Roeck wrote:
On Fri, Aug 30, 2024 at 10:09:25AM +0200, Cédric Le Goater wrote:
Hello,
I solved the problem by adding support for IBM Bonnell (which instantiates
the TPM chip
y: Guenter Roeck
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/sensor/tmp105.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/sensor/tmp105.c b/hw/sensor/tmp105.c
index 6740200aea..f5101af919 100644
--- a/hw/senso
Better to fix than to guess if there are users, I think.
Yes, but it will require some knowledge of s390x, which I cannot provide.
Commit 57da367b9ec4 ("s390x/pci: forbid multifunction pci device") says having
a multifunction device will make the guest spin forever. That is not what Cédric obs
+Matthew +Eric
Side note for the maintainers :
Before this change, the igb device, which is multifunction, was working
fine under Linux.
Was there a fix in Linux since :
57da367b9ec4 ("s390x/pci: forbid multifunction pci device")
6069bcdeacee ("s390x/pci: Move some hotplug checks to the pr
his commit adds that support.
Signed-off-by: Glenn Miles
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/intc/xive.c | 36 ++--
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xiv
additional support for pool interrupts.
Fixes: cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority is more
privileged")
Signed-off-by: Glenn Miles
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/intc/x
On 9/9/24 23:10, Michael Kowal wrote:
From: Frederic Barrat
The 'info pic' HMP command dumps the state of the interrupt controller.
Add the dump of the NVG and NVC tables to its output to ease debug.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by:
eviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/ppc/xive2_regs.h | 1 +
hw/intc/xive2.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 7acf7dccf3..d71a54f9ff 100644
--- a/incl
by the NVT structure indexed by the OS CAM entry.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/ppc/xive2.h | 2 +
include/hw/ppc/xive2_regs.h | 2 +
include/hw/ppc/xive_regs.h | 3 +
hw/intc/xive.c
On 9/10/24 15:34, Michael S. Tsirkin wrote:
On Tue, Sep 10, 2024 at 03:21:54PM +0200, Cédric Le Goater wrote:
On 9/10/24 11:33, Akihiko Odaki wrote:
On 2024/09/10 18:21, Michael S. Tsirkin wrote:
On Fri, Aug 23, 2024 at 02:00:37PM +0900, Akihiko Odaki wrote:
Supersedes: <20240714-rombar-v
On 9/10/24 11:33, Akihiko Odaki wrote:
On 2024/09/10 18:21, Michael S. Tsirkin wrote:
On Fri, Aug 23, 2024 at 02:00:37PM +0900, Akihiko Odaki wrote:
Supersedes: <20240714-rombar-v2-0-af1504ef5...@daynix.com>
("[PATCH v2 0/4] hw/pci: Convert rom_bar into OnOffAuto")
I submitted a RFC series[1]
o the pre_plug
handler")
?
Anyhow,
Tested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/s390x/s390-pci-bus.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
index 3e57d5faca18..00
On 9/6/24 14:25, Guenter Roeck wrote:
Enable UHCI support for ast2400 and ast2500 SoCs. With this patch,
the UHCI port is successfully instantiated on the ast2500-evb machine.
Signed-off-by: Guenter Roeck
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast2400.c | 14
On 9/6/24 14:25, Guenter Roeck wrote:
Enable UHCO support for the ast2600 SoC. With this patch, the UHCI port
is successfully instantiated on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter Roeck
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast2600.c
On 9/6/24 14:25, Guenter Roeck wrote:
Introduce defines for UHCI registers to simplify adding register access
in subsequent patches of the series.
No functional change.
Signed-off-by: Guenter Roeck
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/usb/hcd-uhci.c | 32
On 9/6/24 14:25, Guenter Roeck wrote:
Fix reported checkpatch issues to prepare for next patches
in the series.
No functional change.
Signed-off-by: Guenter Roeck
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/usb/hcd-uhci.c | 90 +--
1
returns 0
tmp105: Lower 4 bit of limit registers are always 0
hw/sensor/tmp105.c | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
For the series,
Reviewed-by: Cédric Le Goater
Thanks,
C.
SPEED_MACHINE,
.class_init= aspeed_machine_rainier_class_init,
+}, {
+.name = MACHINE_TYPE_NAME("bonnell-bmc"),
+.parent = TYPE_ASPEED_MACHINE,
+.class_init= aspeed_machine_bonnell_class_init,
}, {
.name = MACHINE_TYPE_NAME("fuji-bmc"),
.parent= TYPE_ASPEED_MACHINE,
Reviewed-by: Cédric Le Goater
Thanks,
C.
Hello,
On 9/4/24 11:01, Troy Lee wrote:
Hi Cédric,
On Wed, Sep 4, 2024 at 3:29 PM Cédric Le Goater wrote:
Hello Jamin,
Just want you to know that I and Troy are working on the following tasks for
AST2700.
1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35)
Oh nice
umeration constants' prefix to QAPI_VFIO_MIGRATION_STATE.
We could simply drop 'prefix', but then the enumeration constants
would look as if they came from kernel header linux/vfio.h.
Rename the type to QapiVfioMigrationState instead, so that 'prefix' is
not needed.
Signed-off-by: Marku
Hello Jamin,
Just want you to know that I and Troy are working on the following tasks for
AST2700.
1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35)
Oh nice. This is a good topic for heterogeneous machines !
2. Support GPIO.
After we finish above tasks, we will upstream Q
On 9/3/24 10:35, Jamin Lin wrote:
v1:
- support I2C for AST2700
v2:
- fix review issues and add reviewer suggestion
- update avocado test case for AST2700 I2C
- support i2c bus pool
v3:
- update commit messages and commit title
- update API to get the device irq
Jamin Lin (11):
hw/i2c/aspee
bit 15.
I2C bus 0 is connected to GICINT130_INTC at bit 0.
I2C bus 15 is connected to GICINT130_INTC at bit 15.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast27x0.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw
new API to get the INTC orgate input pin
if users only provide the device id with its bus number index.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast27x0.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/hw/arm
herefore, save the high part physical address bit[1:0] of Tx/Rx
buffer address as dma_dram_offset bit[33:32].
It does not need to decrease the dram physical high part address for
DMA operation.
(high part physical address bit[7:0] – 4)
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
Jamin,
On 8/8/24 04:49, Jamin Lin wrote:
Currently, users can set the intc mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous bits number in the
same orgate. To reduce the enumerated device id definition,
create a ne
On 8/8/24 04:49, Jamin Lin wrote:
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado
am_offset bit[33:32].
It does not need to decrease the dram physical
high part address for DMA operation.
(high part physical address bit[7:0] – 4)
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 14 ++
1 file changed, 14 insertions(+)
diff --git
it was done earlier in the
same series.
Thanks,
C.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 48 +
include/hw/i2c/aspeed_i2c.h | 12 +-
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/
Jamin,
In case you resend, would you mind changing the commit title and use
a capital letter on the first word :
hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus
On 8/8/24 04:49, Jamin Lin wrote:
The "Current DMA Operating Address Status(0x50)" register of
I2C new mo
t;DMA Mode Buffer Address Register(I2CD24 old mode)" and
"DMA Operating Address Status (I2CC50 new mode)" are used for showing the
low part dram offset bits [31:0], so change to read/write both register bits
[31:0] in
bus register read/write functions.
Signed-off-by: Jamin Lin
Re
register and pool buffer from the datasheet.
An I2C controller registers owns 8KB address space.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/i2c/aspeed_i2c.c | 62 +
include/hw/i2c/aspeed_i2c.h | 1 +
2 files
: Device 14
0x1000 – 0x107F: Device 15
Introduce a new class attribute to make user set each I2C bus gap size.
Update formula to create all I2C bus register memory regions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/i2c/aspeed_i2c.c | 3 ++-
include
regions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/i2c/aspeed_i2c.c | 3 ++-
include/hw/i2c/aspeed_i2c.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index d3d49340ea..abcb1d5330
On 8/30/24 19:06, Mike Kowal wrote:
On 8/30/2024 3:25 AM, Cédric Le Goater wrote:
On 8/29/24 22:35, Mike Kowal wrote:
On 8/29/2024 7:29 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept
On 8/28/24 15:43, Corvin Köhne wrote:
Hi,
Qemu has experimental support for GPU passthrough of Intels integrated graphic
devices. Unfortunately, Intel has changed some bits for their gen 11 devices
and later. To support these devices, we have to account for those changes. This
patch series adds
On 8/15/24 15:52, Peter Maydell wrote:
The tracepoint trace_vfio_msix_early_setup() uses "int" for the type
of the table_bar argument, but we use this to print a uint32_t.
Coverity warns that this means that we could end up treating it as a
negative number.
We only use this in printing the value
,
but we can keep Coverity happy by doing the shift on
unsigned numbers.
Resolves: Coverity CID 1547742
Signed-off-by: Peter Maydell
Reviewed-by: Cédric Le Goater
Applied to aspeed-next.
Thanks,
C.
On 8/29/24 22:35, Mike Kowal wrote:
On 8/29/2024 7:29 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it
On 8/29/24 22:27, Mike Kowal wrote:
On 8/29/2024 7:14 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Hypervisor "pool" targets do not get their own interrupt line and instead
must share an interrupt line with the hypervisor "physical"
Hello,
I solved the problem by adding support for IBM Bonnell (which instantiates
the TPM chip through its devicetree file, similar to tacoma-bmc) to my local
copy of qemu.
Hmm, did you copy the rainier-bmc machine definition ?
For aspeed_machine_bonnell_class_init(), pretty much yes, sinc
(My s390 box is running Ubuntu, in case that makes a difference.)
Maybe you could put the kernel and initrd somewhere I can
get them from?
I am also trying. See :
https://www.kaod.org/qemu/s390x/
These were generated on my x86/f40 laptop.
C.
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Moved the update to the xive_tctx_set_cppr function which required
addition
On 8/28/24 09:21, Clément Chigot wrote:
On Tue, Aug 27, 2024 at 7:40 PM Cédric Le Goater wrote:
Hello Clément,
On 7/15/24 10:46, Clément Chigot wrote:
The BookE decrementer stops at 0, meaning that it won't decremented
towards "negative" values.
However, the current logic is
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Did you confirm with the HW designer ?
AFAIR, the PIPR is constructed fro
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Hypervisor "pool" targets do not get their own interrupt line and instead
must share an interrupt line with the hypervisor "physical" targets.
This also means that the pool ring must use some of the registers from the
physical ring in the
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified b
On 8/1/24 22:30, Michael Kowal wrote:
From: Frederic Barrat
The 'info pic' HMP command dumps the state of the interrupt controller.
Add the dump of the NVG and NVC tables to its output to ease debug.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/ppc/xive2.h
On 8/1/24 22:29, Michael Kowal wrote:
From: Frederic Barrat
Adds support for single byte writes to offset 0xC18 of the TIMA address
space. When this offset is written to, the hardware disables the OS
context and copies the current state information to the odd cache line
of the pair specified b
On 8/28/24 14:50, Corvin Köhne wrote:
On Wed, 2024-08-28 at 12:40 +0200, Corvin Köhne wrote:
On Mon, 2024-08-26 at 10:35 -0600, Alex Williamson wrote:
PS - please drop the confidential email warning signature when
posting
to public lists.
Sry for the noise. I can't drop it, so I'm going to
On 8/26/24 20:50, Guenter Roeck wrote:
Hi,
On 8/26/24 02:58, Cédric Le Goater wrote:
Hello Guenter,
On 8/9/24 00:05, Guenter Roeck wrote:
Hi,
On Tue, Jun 25, 2024 at 09:08:30AM +0200, Cédric Le Goater wrote:
The tacoma-bmc machine was a board including an AST2600 SoC based BMC
and a
that a new
context is being pushed and fails to check for unpresented
pending interrupts for that context.
Signed-off-by: Glenn Miles
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c | 24 +++-
2
exists
- lwz@0x830 Pull Thread Context to registeradded
lbz@0x838exists
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/ppc/xive_regs.h | 7 ++-
hw
e issue ? which machine ? I didn't see any error
when booting Linux 6.6.3 on mpc8544ds, e500mc, e5500 and e6500.
Signed-off-by: Clément Chigot
Fixed: 8e0a5ac87800 ("hw/ppc: Avoid decrementer rounding errors")
LGTM,
Reviewed-by: Cédric Le Goater
We have some automated tests wit
On 8/7/24 21:51, Alejandro Zeise wrote:
Make the Aspeed HACE module use the new qcrypto accumulative hashing functions
when in scatter-gather accumulative mode. A hash context will maintain a
"running-hash" as each scatter-gather chunk is received.
Previously each scatter-gather "chunk" was cach
Signed-off-by: Peter Maydell
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/vfio/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index 98bd4dccead..c475c273fd8 100644
--- a/hw/vfio/trace-events
+++ b/hw/vf
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