Hello, In the driver for the SMSC LAN9118 device (hw/lan9118.c), I modify the code to update the PM_CTRL register (switch PM_MODE bits to D0 and set (1b) READY bit ) when writing to the BYTE_TEST register.
Writing to PM_CTRL was not permitted before this modification => raise an harware error => QEMU crash when happen. So when you try to perform network connection in u-boot stage in QEMU, QEMU crashed. This way it follow the way the device really work. I add to this email an abstract from the LAN9118 datasheet which explain exactly the modification I made : 3.10.2 Functional Description There is one normal operating power state, D0 and there are two power saving states: D1, and D2. Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed. Patch is contained in the following commit : https://bitbucket.org/bca/qemu-linaro/changeset/0aa1f76e5141 I have sent this patch to qemu-linaro but Peter Maydell (pm215 on #qemu IRC channel) told me to send it here because it is against upstream qemu. Hope I have understood the documentation correctly and that this patch will be helpfull. Sincerely -- Bertrand Cachet, Ingénieur CPE (Lyon, France) Institut REDS, Reconfigurable & Embedded Digital Systems Tél : +41 24/55 77 372 Email : bertrand.cac...@heig-vd.ch<mailto:bertrand.cac...@heig-vd.ch> Internet: http://www.reds.ch HEIG-VD, Haute Ecole d'Ingénierie et de Gestion du Canton de Vaud Rte de Cheseaux 1 CH-1401 Yverdon-les-Bains Internet: http://www.heig-vd.ch
