/20240630120157.259233-1-ra...@linux.ibm.com/
v3 :
https://lore.kernel.org/qemu-devel/20240621114604.868415-1-ra...@linux.ibm.com/
Chinmay Rath (3):
target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc.
target/ppc: Update VMX storage access insns to use
tcg_gen_qemu_ld/st_i128.
target/ppc : Update
Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Introduced functions {get,set}_vsr_full to facilitate the above & for future
use.
Reviewed-by: Richard Henderson
Suggested-by: Richard Henderson
Signed-off-by: Chinmay
Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.
Reviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
target/ppc/translate.c | 10 --
target/ppc
Signed-off-by: Chinmay Rath
---
target/ppc/translate/vmx-impl.c.inc | 42 ++---
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index a182d2cf81..70d0ad2e71 100644
--- a/target/ppc
Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Introduced functions {get,set}_vsr_full to facilitate the above & for future
use.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
target/ppc/translate
Updated instructions {l, st}vx to use tcg_gen_qemu_ld/st_i128,
instead of using 64 bits loads/stores in succession.
Introduced functions {get, set}_avr_full in vmx-impl.c.inc to
facilitate the above, and potential future usage.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
IFALIGN_PAIR memop changes in patches 2/3 and 3/3,
based on review comments by Richard in v1.
v1 :
https://lore.kernel.org/qemu-devel/20240621114604.868415-1-ra...@linux.ibm.com/
Chinmay Rath (3):
target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc.
target/ppc: Update VMX storage access
Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.
Signed-off-by: Chinmay Rath
---
target/ppc/translate.c | 10 --
target/ppc/translate/vmx-impl.c.inc | 10
Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.
Signed-off-by: Chinmay Rath
---
target/ppc/translate.c | 10 --
target/ppc/translate/vmx-impl.c.inc | 10
Updated instructions {l, st}vx to use tcg_gen_qemu_ld/st_i128,
instead of using 64 bits loads/stores in succession.
Introduced functions {get, set}_avr_full in vmx-impl.c.inc to
facilitate the above, and potential future usage.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Introduced functions {get,set}_vsr_full to facilitate the above & for future
use.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
target/ppc/translate
Updating a bunch of VMX and VSX storage access instructions to use
tcg_gen_qemu_ld/st_i128 instead of using tcg_gen_qemu_ld/st_i64 in
succession; as suggested by Richard, in my decodetree patches.
Plus some minor clean-ups to facilitate the above in case of VMX insns.
Chinmay Rath (3):
target
: Unified helper calls.
- Retained Richard's "Reviewed-by" in patches 1, 3 and 4.
v1:
https://lore.kernel.org/qemu-devel/20240607144921.726730-1-ra...@linux.ibm.com/
Chinmay Rath (4):
target/ppc: Moving VSX scalar storage access insns to decodetree.
target/ppc: Move VSX vector w
captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode| 13 +
target/ppc/translate/vsx-impl.c.inc | 79 +
target/ppc/translate/vsx-ops.c.inc | 11
3 files changed, 49
Moving the following instructions to decodetree specification:
xvcmp{eq, gt, ge, ne}{s, d}p: XX3-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay
,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode| 10 ++
target/ppc/translate/vsx-impl.c.inc | 199
target/ppc/translate/vsx-ops.c.inc | 12 --
3 files changed, 97 insertions(+), 124 deletions(-)
diff
do_ea_calc_ra to calculate the effective address :
EA <- (RA == 0) ? 0 : GPR[RA], which is now used by the above-said insns,
and shall be used later by (p){lx, stx}vp insns.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h | 8 +--
target/ppc/insn32.decode| 6 ++
tar
On 6/17/24 23:27, Richard Henderson wrote:
On 6/17/24 04:51, Chinmay Rath wrote:
Hi Richard,
On 6/17/24 00:43, Richard Henderson wrote:
On 6/13/24 02:33, Chinmay Rath wrote:
+/* EA <- (ra == 0) ? 0 : GPR[ra] */
+static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
+{
+ TCGv
On 6/17/24 23:15, Richard Henderson wrote:
On 6/17/24 03:40, Chinmay Rath wrote:
static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
{
TCGv EA;
if (!ra) {
return tcg_constant_tl(0);
}
if (NARROW_MODE(ctx)) {
EA = tcg_temp_new
Hi Richard,
On 6/17/24 00:43, Richard Henderson wrote:
On 6/13/24 02:33, Chinmay Rath wrote:
+/* EA <- (ra == 0) ? 0 : GPR[ra] */
+static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
+{
+ TCGv EA;
+ if (!ra) {
+ EA = tcg_constant_tl(0);
+ return EA;
+ }
+
Hi Richard,
On 6/17/24 00:43, Richard Henderson wrote:
On 6/13/24 02:33, Chinmay Rath wrote:
+/* EA <- (ra == 0) ? 0 : GPR[ra] */
+static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
+{
+ TCGv EA;
+ if (!ra) {
+ EA = tcg_constant_tl(0);
+ return EA;
+ }
+
Moving the following instructions to decodetree specification:
xvcmp{eq, gt, ge, ne}{s, d}p: XX3-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay
for ea calculation instead of inlining,
for later use by (p){lx,stx}vp insns.
- Patch 4/4 : Unified helper calls.
- Retained Richard's "Reviewed-by" in patches 1, 3 and 4.
v1:
https://lore.kernel.org/qemu-devel/20240607144921.726730-1-ra...@linux.ibm.com/
Chinmay Rath (4):
captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode| 13 +
target/ppc/translate/vsx-impl.c.inc | 79 +
target/ppc/translate/vsx-ops.c.inc | 11
3 files changed, 49
,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode| 10 ++
target/ppc/translate/vsx-impl.c.inc | 199
target/ppc/translate/vsx-ops.c.inc | 12 --
3 files changed, 97 insertions(+), 124 deletions(-)
diff
to calculate the effective address :
EA <- (RA == 0) ? 0 : GPR[RA], which is now used by the above-said insns,
and shall be used later by (p){lx, stx}vp insns.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h | 8 +--
target/ppc/insn32.decode| 6 ++
target/
Hi Richard,
My apologies for the ill formatted reply in this patch series. Just
realized it now. The cliched 'Tab' issue with the mail client XD.
On 6/7/24 21:16, Richard Henderson wrote:
On 6/7/24 07:49, Chinmay Rath wrote:
Moving the following instructions to decodetree specification
On 6/7/24 21:25, Richard Henderson wrote:
On 6/7/24 07:49, Chinmay Rath wrote:
+static bool do_cmp(DisasContext *ctx, arg_XX3_rc *a,
+ void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr,
TCGv_ptr))
+{
+ TCGv_i32 ignored;
+ TCGv_ptr xt, xa, xb;
+ REQUIRE_VSX(ctx
Hi Richard,
On 6/7/24 21:16, Richard Henderson wrote:
On 6/7/24 07:49, Chinmay Rath wrote:
Moving the following instructions to decodetree specification:
lxv{b16, d2, h8, w4, ds, ws}x : X-form
stxv{b16, d2, h8, w4}x : X-form
The changes were verified by validating
Hi Richard,
On 6/7/24 21:11, Richard Henderson wrote:
On 6/7/24 07:49, Chinmay Rath wrote:
+static bool do_ld_st_vl(DisasContext *ctx, arg_X *a,
+ void (*helper)(TCGv_ptr, TCGv, TCGv_ptr, TCGv))
+{
+ TCGv EA;
+ TCGv_ptr xt;
+ if (a->rt &
Moving all remaining VSX storage access instructions and all VSX compare
instructions of XX3 form with RC field, to decodetree specification.
Chinmay Rath (4):
target/ppc: Moving VSX scalar storage access insns to decodetree.
target/ppc: Move VSX vector with length storage access insns
,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32.decode| 10 ++
target/ppc/translate/vsx-impl.c.inc | 199
target/ppc/translate/vsx-ops.c.inc | 12 --
3 files changed, 97 insertions(+), 124 deletions(-)
diff --git a/target/ppc/insn32.decode
captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32.decode| 13 +
target/ppc/translate/vsx-impl.c.inc | 79 +
target/ppc/translate/vsx-ops.c.inc | 11
3 files changed, 49 insertions(+), 54 deletions(-)
diff
Moving the following instructions to decodetree specification:
xvcmp{eq, gt, ge, ne}{s, d}p: XX3-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay
Moving the following instructions to decodetree specification :
{l, st}xvl(l) : X-form
The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
-off-by: Chinmay Rath
---
target/ppc/insn32.decode| 11
target/ppc/translate/vsx-impl.c.inc | 39 +
target/ppc/translate/vsx-ops.c.inc | 11
3 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/target/ppc/insn32.decode b/target
Moving PPC2_ISA300 flag check out of do_helper_XX3 method in vmx-impl.c.inc
so that the helper can be used with other instructions as well.
Signed-off-by: Chinmay Rath
---
target/ppc/translate/vsx-impl.c.inc | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git
Moving a number of VSX arithmetic, max/min and logical instructions to
decodetree specification.
Also moving ISA300 flag check in the do_helper_XX3 methods in
vsx-impl.c.inc file; out of it, to make it usable for a larger num of
instructions.
Chinmay Rath (3):
target/ppc: Move ISA300 flag
captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h | 44 ++--
target/ppc/insn32.decode| 30 ++
target/ppc/fpu_helper.c | 44 ++--
target/ppc/translate/vsx-impl.c.inc | 63
No need for a full comparison; xor produces non-zero bits for QC just fine.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
target/ppc/translate/vmx-impl.c.inc | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
patch to improve the moved insns as per suggestion by
Richard in v1.
v1:
https://lore.kernel.org/qemu-devel/20240512093847.18099-1-ra...@linux.ibm.com/
Chinmay Rath (2):
target/ppc: Move VMX integer add/sub
Moving the following instructions to decodetree specification :
v{add,sub}{u,s}{b,h,w}s : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay
Hi Richard,
On 5/12/24 17:08, Richard Henderson wrote:
On 5/12/24 11:38, Chinmay Rath wrote:
@@ -2934,6 +2870,184 @@ static bool do_vx_vaddsubcuw(DisasContext
*ctx, arg_VX *a, int add)
return true;
}
+static inline void do_vadd_vsub_sat
+(
+ unsigned vece, TCGv_vec t, TCGv_vec
Hi Richard,
On 5/12/24 15:59, Richard Henderson wrote:
On 5/12/24 11:38, Chinmay Rath wrote:
1. vsubsbs and bcdtrunc :
In this pair, bcdtrunc has the insn flag check PPC2_ISA300 in the
vmx-impl file, within the GEN_VXFORM_DUAL macro, which does this flag
check.
However it also has this flag
,
Chinmay
Chinmay Rath (1):
target/ppc: Move VMX integer add/sub saturate insns to decodetree.
target/ppc/helper.h | 24 +--
target/ppc/insn32.decode| 16 ++
target/ppc/int_helper.c | 22 +--
target/ppc/translate/vmx-impl.c.inc | 242
Moving the following instructions to decodetree specification :
v{add,sub}{u,s}{b,h,w}s : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay
On 5/1/24 18:34, Nicholas Piggin wrote:
Memory barriers are supposed to do something on BookE systems, these
were probably just missed during MTTCG enablement, maybe no targets
support SMP. Either way, add proper BookE implementations.
Signed-off-by: Nicholas Piggin
Reviewed-by: Chinmay
On 5/1/24 18:34, Nicholas Piggin wrote:
POWER10 adds a new field to sync for store-store syncs, and some
new variants of the existing syncs that include persistent memory.
Implement the store-store syncs and plwsync/phwsync.
Signed-off-by: Nicholas Piggin
Reviewed-by: Chinmay Rath
fields. The existing behaviour causes illegal instruction exceptions
when using new POWER10 sync variants that add new fields, after this
the instructions are accepted and are implemented as supersets of
the new behaviour, as intended.
Signed-off-by: Nicholas Piggin
Reviewed-by: Chinmay Rath
-by: Chinmay Rath
---
target/ppc/insn32.decode| 11 +++
target/ppc/translate/vmx-impl.c.inc | 22 ++
target/ppc/translate/vmx-ops.c.inc | 15 ---
3 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/target/ppc/insn32.decode b/target
in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h | 12 +-
target/ppc/insn32.decode| 17 +++
target/ppc/mem_helper.c | 12 +-
target/ppc/translate.c | 2 -
target/ppc/translate/vmx-impl.c.inc | 221
Moving VMX instructions of the following types to decodetree
specification : storage access, integer logical & integer max/min.
Chinmay Rath (3):
target/ppc: Move VMX storage access instructions to decodetree
target/ppc: Move VMX integer logical instructions to decodetree
target/ppc:
Moving the following instructions to decodetree specification :
v{max, min}{u, s}{b, h, w, d} : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay
' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/helper.h| 4 +-
target/ppc/insn32.decode | 8
target/ppc/int_helper.c| 4 +-
target/ppc/translate.c | 56
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
/20240416063927.99428-1-ra...@linux.ibm.com/
Chinmay Rath (8):
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
target/ppc: Make divw[u] handler method decodetree compatible.
target/ppc: Move divw[u, e, eu] instructions to decodetree.
target/ppc: Move neg, darn, mod{sw, uw
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard
generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also, remaned do_divwe method in fixedpoint-impl.c.inc to do_dive because it is
now used to divide doubleword operands as well, and not just words.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard
-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/helper.h| 6 +-
target/ppc/insn32.decode | 16 +++
target/ppc/excp_helper.c | 4 +-
target/ppc/int_helper.c| 2 +-
target/ppc/translate.c
with the '-d in_asm,op' flag.
Also cleaned up code for mullw[o][.] as per review comments while
keeping the logic of the tcg ops generated semantically same.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode | 9 +++
target/ppc/translate.c
,op'
flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode | 9 ++
target/ppc/translate.c | 101 -
target/ppc/translate/fixedpoint-impl.c.inc | 85 +
3 files changed, 94 insertions
le, so that the
mentioned insns can be safely move to decodetree specs.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
---
target/ppc/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c455
Hi Richard,
On 4/20/24 21:21, Richard Henderson wrote:
On 4/19/24 02:25, Chinmay Rath wrote:
Hi Richard,
On 4/17/24 00:06, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
+static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
...
+ tcg_gen_movi_i64(t1, 0);
Drop
On 4/17/24 00:08, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.] : XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved
On 4/17/24 01:05, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s] : D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d
Hi Richard,
On 4/17/24 00:50, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
isel : A-form
The changes were verified by validating
Hi Richard,
On 4/17/24 00:06, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
+static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
...
+ tcg_gen_movi_i64(t1, 0);
Drop the movi.
+ tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo, hi, cpu_gpr[a->rc], t1);
On 4/16/24 23:55, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by
those
On 4/16/24 23:49, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by
those
instructions remain the same
Hi Richard,
On 4/16/24 23:27, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
The handler methods for divw[u] instructions internally use
Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if
we move
the above said instructions to decodet
Hi Richard,
On 4/16/24 23:26, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.] : XO-form
The changes were verified by validating that the tcg
, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 6 +-
target/ppc/insn32.decode | 16 +++
target/ppc/excp_helper.c | 4 +-
target/ppc/int_helper.c| 2
,op'
flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32.decode | 9 ++
target/ppc/translate.c | 101 -
target/ppc/translate/fixedpoint-impl.c.inc | 85 +
3 files changed, 94 insertions(+), 101 deletions(-)
diff
with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32.decode | 9 +++
target/ppc/translate.c | 89 --
target/ppc/translate/fixedpoint-impl.c.inc | 71 +
3 files changed, 80 insertions(+), 89 deletions
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 4 +-
target/ppc/insn32.decode | 8
target/ppc/int_helper.c| 4 +-
target/ppc/translate.c | 56 --
target/ppc/translate/fixedpoint
generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also, remaned do_divwe method in fixedpoint-impl.c.inc to do_dive because it is
now used to divide doubleword operands as well, and not just words.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h
le, so that the
mentioned insns can be safely move to decodetree specs.
Signed-off-by: Chinmay Rath
---
target/ppc/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c45547a770..be7d807e3c 100644
--- a/targ
Moving all fixed-point instructions of the following type to decodetree
specification : arithmetic, compare, trap, select and logical.
Chinmay Rath (8):
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
target/ppc: Make divw[u] handler method decodetree compatible
been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Nicholas Piggin
---
target/ppc/helper.h| 44
This patch merges the definitions of the following set of fpu helper methods,
which are similar, using macros :
1. f{add, sub, mul, div}(s)
2. fre(s)
3. frsqrte(s)
Signed-off-by: Chinmay Rath
---
target/ppc/fpu_helper.c | 221 +++-
1 file changed, 62
to decodetree.
Change log :
v2 : Addressed review comments on v1
v1 :
https://lore.kernel.org/qemu-devel/20240307110318.170319-1-ra...@linux.ibm.com/
Chinmay Rath (2):
target/ppc: Merge various fpu helpers
target/ppc: Move floating-point arithmetic instructions to decodetree.
target/ppc/helper.h
On 3/12/24 15:31, Nicholas Piggin wrote:
On Thu Mar 7, 2024 at 9:03 PM AEST, Chinmay Rath wrote:
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index 189cd8c979..03b84ba79b 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp
On 3/12/24 19:59, Peter Maydell wrote:
On Tue, 12 Mar 2024 at 14:25, Nicholas Piggin wrote:
On Wed Mar 13, 2024 at 12:01 AM AEST, Richard Henderson wrote:
On 3/11/24 23:36, Nicholas Piggin wrote:
[snip]
#define FPU_HELPER(name, op, flags_handler) \
float64
in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 44 ++---
target/ppc/insn32.decode | 42 +
target/ppc/fpu_helper.c| 265 +-
target/ppc/translate/fp-impl.c.inc | 288 +++--
target/ppc
specification, for
which all the four variations([o][.]) have been handled with a single pattern.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
Changes v1 ->
Hi Richard,
On 2/13/24 03:51, Richard Henderson wrote:
On 2/9/24 01:35, Chinmay Rath wrote:
+_tab_cy rt ra rb cy
+@Z23_tab_cy .. rt:5 ra:5 rb:5 cy:2 . _tab_cy
...
+ADDEX 01 . . . .. 10101010 - @Z23_tab_cy
...
+static bool trans_ADDEX
specification, for
which all the four variations([o][.]) have been handled with a single pattern.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/insn32
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