d only be 0 or 1 in user mode, or
it will cause target SEGV (and the patch doesn't implement system mode).
You correctly modified the change to raise SIGILL, so you should
also update the commit message the same way.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
On 10/1/2015 10:26 PM, Richard Henderson wrote:
On 10/02/2015 11:31 AM, Chris Metcalf wrote:
It disables interrupts from being delivered. This means asynchronous
interrupts get deferred until ICS is set back to zero, and synchronous
interrupts (page fault, etc) cause a double-fault instead
t the interrupt mask prior to
returning.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
,
MF_UNARY_OPCODE_X1 = 31,
MM_BF_OPCODE_X0 = 7,
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
These particular opcode names are not used in the kernel directly,
so updating them just has the effect of making downstream consumers
more like to end up using better names; this was reported from the
qemu community.
Reported-by: Richard Henderson r...@twiddle.net
Signed-off-by: Chris Metcalf
to provide related pdf documents, if possible.
I worked with our internal folks to get a few more tilegx hardware docs
on the web site:
http://www.ezchip.com/scm/docs/
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
I will be posting more hardware documents on Wednesday when I'm back in the
office.
On Jun 4, 2015, at 5:33 AM, Chen Gang xili_gchen_5...@hotmail.com wrote:
On 06/03/2015 11:47 PM, Richard Henderson wrote:
On 06/03/2015 05:34 AM, Peter Maydell wrote:
You must do something. You can't
On 06/03/2015 11:19 AM, Peter Maydell wrote:
On 3 June 2015 at 16:10, Chris Metcalf cmetc...@ezchip.com wrote:
On 06/03/2015 08:47 AM, Chen Gang wrote:
On 06/03/2015 08:34 PM, Peter Maydell wrote:
You must do something. You can't allow guest code (even
broken guest code) to make QEMU assert
internally, and userspace
applications can use udn0..udn3 after setting up a suitable
hardwall with the kernel (see arch/tile/kernel/hardwall.c), but
you almost certainly don't want to care about any of that.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
Congratulations!
On May 21, 2015, at 4:58 PM, Chen Gang xili_gchen_5...@hotmail.com wrote:
After fix additional 3 bugs (one for mnz, one for mz, one for v1cmpeqi),
at present, tilegx linux user can print Hello World! :-)
I shall reconstruct/prepare the code and send patch v11 for review
the TILE-Gx chip series.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
.
What about CPU models? Do the Gx72, Gx36, etc. differ only in core count
or also in instruction set features?
From a userspace perspective, it's mostly the core count. They also have a
different set of on-chip hardware accelerators, etc., but that's out of scope
for this project.
--
Chris
ops.
There is only one memory op possible per bundle.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
of the code, and I only skimmed it
quickly, but generally: good work getting as far as you have!
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
familiar with the arch/opcode.h naming, and reduces the amount of code needed
to review qemu in any case.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
and review.
Then later when you use them they are self-documenting. And if you
are going to use opcode_tilegx.h anyway, you get the names for free.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
On 2/19/2015 7:07 PM, Chen Gang S wrote:
+#ifdef TARGET_NR_chown /* not on tilegx */
I would omit all these comments. The same will be true for arm64, microblaze,
or any other kernel architecture submitted after the tile architecture went in.
--
Chris Metcalf, EZChip Semiconductor
http
disassembly that Chen Gang is looking at is basically just an
instruction recognizer; it doesn't even include text strings for opcodes,
for example. But my guess is that it is exactly the right starting building
block for decoding target binary instructions.
--
Chris Metcalf, EZChip Semiconductor
http
can
issue a lnk REG instruction to load the address of the following register
into register REG. And if you have interrupted the machine execution
with an interrupt or fault, you will find the interrupted address in an SPR.
But the current PC is not otherwise accessible.
--
Chris Metcalf, EZChip
, too.
Thanks.
On 2/14/15 23:53, Chen Gang S wrote:
On 2/14/15 13:47, Peter Maydell wrote:
On 14 February 2015 at 03:37, Chris Metcalf cmetc...@ezchip.com wrote:
I'm not sure whether Tilera can simply re-release the tilegx-specific stuff
from binutils as a separate tarball with GPL v2 licensing
, Peter Maydell wrote:
On 14 February 2015 at 03:37, Chris Metcalf cmetc...@ezchip.com wrote:
I'm not sure whether Tilera can simply re-release the tilegx-specific stuff
from binutils as a separate tarball with GPL v2 licensing. Hopefully we can
avoid having to figure that out. :-)
I believe
. :-)
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
, so it probably doesn't do you much good. If you're interested,
I can send you the diffs.
Welcome the related diffs, I guess, it must be helpful. :-)
I uploaded it to:
http://173.201.26.195/scm/qemu-kvm-0.13.0.get
Notice that this is against a much older version of qemu, though.
--
Chris
use the same name
here, not EM_TILE.
Oh, I can not fine EM_TILEGX in elf.h in master branch. I guess, I
need to define it, too.
It is in glibc's /usr/include/elf.h since version 2.16.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
intended to be used with KVM for
virtualization, so it probably doesn't do you much good. If you're interested,
I can send you the diffs.
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
code cleanliness.
--
Chris Metcalf, Tilera Corp.
http://www.tilera.com
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