Re: [PATCH v2 2/2] hw/sparc/leon3: add second uart with extended interrupt usage

On Sat, Sep 21, 2024 at 6:43 PM Nikita Shushura wrote: > > Signed-off-by: Nikita Shushura Mostly OK just a few comments. > --- > hw/sparc/leon3.c | 63 +++- > 1 file changed, 46 insertions(+), 17 deletions(-) > > diff --git a/hw/sparc/leon3.c b/hw/sp

Re: [PATCH v2 1/2] hw/intc/grlib_irqmp: add support for extended interrupts

On Sat, Sep 21, 2024 at 6:43 PM Nikita Shushura wrote: > > Signed-off-by: Nikita Shushura Additionally to inlined comments: - there are a few "extended (not supported)" you can now remove. - I think the extended part in "grlib_irqmp_write" is still wrong, the extended register being read-only.

Re: [PATCH] hw/ppc: fix decrementer with BookE timers

Hi Cédric, On Tue, Aug 27, 2024 at 7:40 PM Cédric Le Goater wrote: > > Hello Clément, > > On 7/15/24 10:46, Clément Chigot wrote: > > The BookE decrementer stops at 0, meaning that it won't decremented > > towards "negative" values. > > However, t

Re: [PATCH] hw/ppc: fix decrementer with BookE timers

On Thu, Aug 29, 2024 at 2:33 PM Cédric Le Goater wrote: > > On 8/28/24 09:21, Clément Chigot wrote: > > On Tue, Aug 27, 2024 at 7:40 PM Cédric Le Goater wrote: > >> > >> Hello Clément, > >> > >> On 7/15/24 10:46, Clément Chigot wrote: > >>

Re: [PATCH] hw/ppc: fix decrementer with BookE timers

On Tue, Aug 27, 2024 at 7:40 PM Cédric Le Goater wrote: > > Hello Clément, > > On 7/15/24 10:46, Clément Chigot wrote: > > The BookE decrementer stops at 0, meaning that it won't decremented > > towards "negative" values. > > However, the current l

Re: [PATCH] hw/ppc: fix decrementer with BookE timers

Hey, Gentle ping Thanks Clément On Mon, Jul 29, 2024 at 10:33 AM Clément Chigot wrote: > > Hi, > > Gentle ping + CC missing maintainers. > > Thanks Clément > > On Mon, Jul 15, 2024 at 10:46 AM Clément Chigot wrote: > > > > The BookE decrementer stops at

Re: [PATCH] hw/ppc: fix decrementer with BookE timers

Hi, Gentle ping + CC missing maintainers. Thanks Clément On Mon, Jul 15, 2024 at 10:46 AM Clément Chigot wrote: > > The BookE decrementer stops at 0, meaning that it won't decremented > towards "negative" values. > However, the current logic is inverted: decr i

[PATCH] hw/ppc: fix decrementer with BookE timers

The BookE decrementer stops at 0, meaning that it won't decremented towards "negative" values. However, the current logic is inverted: decr is updated solely when the resulting value would be negative. Signed-off-by: Clément Chigot Fixed: 8e0a5ac87800 ("hw/ppc: Avoid decreme

Re: [PATCH] tests/avocado: Remove non-working sparc leon3 test

can restore the > > file from an older version of QEMU. > > > > Signed-off-by: Thomas Huth > > Acked-by: Alex Bennée Yeah, it's been on my todo list for far too long but I still didn't find time to work on it. Reviewed-by: Clément Chigot

Re: [PULL 13/42] target/i386: use gen_writeback() within gen_POP()

On Wed, Jul 10, 2024 at 12:43 PM Paolo Bonzini wrote: > > On 7/10/24 11:42, Clément Chigot wrote: > > Hi Mark, > > > > This patch introduces regressions in our x86_64 VxWorks kernels > > running over qemu. Some page faults are triggered randomly. > > >

Re: [PULL 13/42] target/i386: use gen_writeback() within gen_POP()

Hi Mark, This patch introduces regressions in our x86_64 VxWorks kernels running over qemu. Some page faults are triggered randomly. Earlier to this patch, the MemOp `ot` passed to `gen_op_st_v` was the `gen_pop_T0` created a few lines above. Now, this is `op->ot` which comes from elsewhere. Add

[PATCH] target/sparc: use signed denominator in sdiv helper

The result has to be done with the signed denominator (b32) instead of the unsigned value passed in argument (b). Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV") Signed-off-by: Clément Chigot --- target/sparc/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) di

Re: [PATCH] target/arm: Restrict translation disabled alignment check to VMSA

. > >> > >> Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when > >> translation disabled") > >> Reported-by: Clément Chigot > >> Signed-off-by: Richard Henderson > >> --- > >> > >> Since v9 will l

Re: [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled

Hi Richard, While testing the future V9, I've some regressions on a custom board using cortex-R5 CPUs. Unaligned data accesses are no longer allowed because of that patch. I've dug into the various documentation and it seems that R-profile CPUs don't have the same default memory type as A-profile

Re: [PATCH for-9.0] target/riscv: do not enable all named features by default

block sizes so it'll retain its own flag and entry. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2024-03/msg02592.html > > Reported-by: Clément Chigot > Fixes: 3b8022269c ("target/riscv: add riscv,isa to named features") > Suggested-by: Andrew Jones > Signed-of

Re: [PULL 09/34] target/riscv: add remaining named features

Hi Alistair, Since this series, I'm getting warnings when using a CPU not supporting the latest ISA, such as the SIFIVE_E series. | $ qemu-system-riscv32 -M sifive_e | qemu-system-riscv32: warning: disabling zic64b extension for hart 0x because privilege spec version does not match

[PATCH] hw/intc/grlib_irqmp: abort realize when ncpus value is out of range

Even if the error is set, the build is not aborted when the ncpus value is wrong, the return is missing. Signed-off-by: Clément Chigot --- hw/intc/grlib_irqmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 144b121d48..c6c51a349c 100644

Re: [PULL 34/56] hw/intc/grlib_irqmp: add ncpus property

On Fri, Mar 8, 2024 at 2:27 PM Peter Maydell wrote: > > On Thu, 15 Feb 2024 at 18:04, Philippe Mathieu-Daudé > wrote: > > > > From: Clément Chigot > > > > This adds a "ncpus" property to the "grlib-irqmp" device to be used > > later,

Re: QNX VM hang on Qemu

hat such a command exists. However, the --run option seems to call the script "runimage". You might want to take a look at the options being set or maybe simply retrieve the qemu command line created by it (if that's not how you created your first command line). Sorry to not be more

Re: QNX VM hang on Qemu

Hi Faiq, On Fri, Feb 23, 2024 at 3:55 PM Faiq Ali Sayed wrote: > > So as far as my understanding, we provide these binaries using Qemu command > as depicted in the example you provided and there is no way I found to put > them into a single image. > Regarding the overlapping space, I don't have

Re: [PATCH] hw/sparc/leon3: Fix wrong usage of DO_UPCAST macro

Hi Philippe, Thomas Thanks for handling that ! And I do confirm that it does not trigger any obvious regression on our side. Thanks, Clément On Thu, Feb 22, 2024 at 8:46 AM Philippe Mathieu-Daudé wrote: > > On 21/2/24 19:49, Philippe Mathieu-Daudé wrote: > > On 21/2/24 19:47, Philippe Mathieu-D

Re: [PATCH 3/3] meson: Enable -Wvla

On Wed, Feb 21, 2024 at 6:27 PM Philippe Mathieu-Daudé wrote: > > On 21/2/24 17:59, Thomas Huth wrote: > > On 21/02/2024 17.26, Thomas Huth wrote: > >> From: Peter Maydell > >> > >> QEMU has historically used variable length arrays only very rarely. > >> Variable length arrays are a potential sec

Re: [PATCH v3 0/9] sparc/leon3: Add support for -smp

Hi Philippe On Thu, Feb 15, 2024 at 10:02 AM Philippe Mathieu-Daudé wrote: > > Hi Clément, > > On 31/1/24 09:50, Clément Chigot wrote: > > > This series allows leon3 emulations to record up 4 CPUs. > > > Clément Chigot (9): > >sparc/grlib: split

[PATCH v3 2/9] intc/grlib_irqmp: add ncpus property

This adds a "ncpus" property to the "grlib-irqmp" device to be used later, this required a little refactoring of how we initialize the device (ie: use realize instead of init). Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu

[PATCH v3 6/9] leon3: remove SP initialization

According to the doc (see §4.2.15 in [1]), the reset operation should not impact %SP. [1] https://gaisler.com/doc/gr712rc-usermanual.pdf Signed-off-by: Clément Chigot --- hw/sparc/leon3.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 7866f0a049

[PATCH v3 4/9] intc/grlib_irqmp: implements multicore irq

Now there is an ncpus property, use it in order to deliver the IRQ to multiple CPU. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/grlib_irqmp.c | 41 +-- hw/sparc/leon3.c | 3

[PATCH v3 7/9] leon3: implement multiprocessor

This allows to register more than one CPU on the leon3_generic machine. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/sparc/leon3.c | 98 ++-- 1 file changed, 70 insertions(+), 28 deletions(-) diff --git a/hw/sparc/leon3.c b

[PATCH v3 0/9] sparc/leon3: Add support for -smp

been tested locally with various bareboard runtimes. CC: Frederic Konrad (maintainer:Leon3) CC: Mark Cave-Ayland (maintainer:SPARC TCG CPUs) CC: Artyom Tarasenko (maintainer:SPARC TCG CPUs) CC: Philippe Mathieu-Daudé Clément Chigot (9): sparc/grlib: split out the headers for each

[PATCH v3 5/9] target/sparc: implement asr17 feature for smp

This allows the guest program to know its cpu id. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/helper.c| 16 target/sparc/helper.h| 1 + target/sparc/translate.c

[PATCH v3 3/9] intc/grlib_irqmp: implements the multiprocessor status register

Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/grlib_irqmp.c | 35 --- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 744cd64c58..1e073bd232 100644 --- a/hw/intc

[PATCH v3 8/9] leon3: check cpu_id in the tiny bootloader

Now that SMP is possible, the asr17 must be checked in the little boot code or the secondary CPU will reinitialize the Timer and the Uart. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé --- hw/sparc/leon3.c | 22 -- 1

[PATCH v3 9/9] MAINTAINERS: replace Fabien by myself as Leon3 maintainer

CC: Fabien Chouteau Signed-off-by: Clément Chigot Reviewed-by: Fabien Chouteau --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index dfaca8323e..f076c97fcb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1708,7 +1708,7 @@ F: hw/rtc

[PATCH v3 1/9] sparc/grlib: split out the headers for each peripherals

... and move them in their right hardware directory. Update Copyright and add SPDX-License-Identifier at the same time. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé --- hw/char/grlib_apbuart.c | 6 ++-- hw/intc

Re: [PATCH 2/2] hw/sparc/leon3: Remove duplicated code

hw_init(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/sparc/leon3.c | 2 -- > 1 file changed, 2 deletions(-) Thanks for those cleanups ! Reviewed-by: Clément Chigot > diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c > index 2dfb742566..1ae9a37583 100644 >

Re: [PATCH 1/2] target/sparc: Provide hint about CPUSPARCState::irq_manager member

/sparc/cpu.h | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) Reviewed-by: Clément Chigot > diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h > index 12a11ecb26..d02684569a 100644 > --- a/target/sparc/cpu.h > +++ b/target/sparc/cpu.h > @@ -548,10 +548,9 @@ struct CP

Re: [PATCH v2 6/8] leon3: implement multiprocessor

On Tue, Jan 30, 2024 at 12:43 PM Philippe Mathieu-Daudé wrote: > > Hi Clément, > > On 16/1/24 14:02, Clément Chigot wrote: > > This allows to register more than one CPU on the leon3_generic machine. > > > > Co-developed-by: Frederic Konrad > > Signed-off-

Re: [PATCH v2 7/8] leon3: check cpu_id in the tiny bootloader

On Tue, Jan 30, 2024 at 10:15 AM Philippe Mathieu-Daudé wrote: > > On 16/1/24 14:02, Clément Chigot wrote: > > Now that SMP is possible, the asr17 must be checked in the little boot code > > or the secondary CPU will reinitialize the Timer and the Uart. > > > > Co

Re: [PATCH v2 0/8] sparc/leon3: Add support for -smp

Hey Philippe, Gentle ping on this serie Thanks, Clément On Tue, Jan 16, 2024 at 2:02 PM Clément Chigot wrote: > > V2 modifications > - Patch1: Add SPDX copyright tags. > - Patch3: Add defines for MP_STATUS fields. Improve comments. > - Patch4: Improve a comment. > -

[PATCH v2 5/8] target/sparc: implement asr17 feature for smp

This allows the guest program to know its cpu id. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Richard Henderson --- target/sparc/helper.c| 16 target/sparc/helper.h| 1 + target/sparc/translate.c | 13 +++-- 3 files changed, 20

[PATCH v2 8/8] MAINTAINERS: replace Fabien by myself as Leon3 maintainer

CC: Fabien Chouteau Signed-off-by: Clément Chigot Reviewed-by: Fabien Chouteau --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index b406fb20c0..b4e78e7748 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1708,7 +1708,7 @@ F: hw/rtc

[PATCH v2 7/8] leon3: check cpu_id in the tiny bootloader

Now that SMP is possible, the asr17 must be checked in the little boot code or the secondary CPU will reinitialize the Timer and the Uart. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/sparc/leon3.c | 22 -- 1 file changed, 20 insertions(+), 2

[PATCH v2 6/8] leon3: implement multiprocessor

This allows to register more than one CPU on the leon3_generic machine. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/sparc/leon3.c | 106 +-- 1 file changed, 74 insertions(+), 32 deletions(-) diff --git a/hw/sparc/leon3.c b

[PATCH v2 3/8] intc/grlib_irqmp: implements the multiprocessor status register

Signed-off-by: Clément Chigot --- hw/intc/grlib_irqmp.c | 35 --- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 744cd64c58..fa689e7a1f 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc

[PATCH v2 4/8] intc/grlib_irqmp: implements multicore irq

Now there is an ncpus property, use it in order to deliver the IRQ to multiple CPU. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/intc/grlib_irqmp.c | 43 ++- hw/sparc/leon3.c | 3 ++- include/hw/intc/grlib_irqmp.h

[PATCH v2 2/8] intc/grlib_irqmp: add ncpus property

This adds a "ncpus" property to the "grlib-irqmp" device to be used later, this required a little refactoring of how we initialize the device (ie: use realize instead of init). Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu

[PATCH v2 1/8] sparc/grlib: split out the headers for each peripherals

... and move them in their right hardware directory. Update Copyright and add SPDX-License-Identifier at the same time. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/char/grlib_apbuart.c | 6 ++-- hw/intc/grlib_irqmp.c

[PATCH v2 0/8] sparc/leon3: Add support for -smp

device and adding the cpu_index field in the asr17 instruction. It has been tested locally with various bareboard runtimes. Clément Chigot (8): sparc/grlib: split out the headers for each peripherals intc/grlib_irqmp: add ncpus property intc/grlib_irqmp: implements the multiprocessor status

Re: [PATCH 1/9] sparc/grlib: split out the headers for each peripherals

On Fri, Jan 5, 2024 at 3:00 PM Philippe Mathieu-Daudé wrote: > > On 5/1/24 11:24, Clément Chigot wrote: > > ... and move them in their right hardware directory. > > > > Co-developed-by: Frederic Konrad > > Signed-off-by: Clément Chigot > &g

Re: [PATCH 3/9] intc/grlib_irqmp: implements the multiprocessor status register

On Fri, Jan 5, 2024 at 2:37 PM Philippe Mathieu-Daudé wrote: > > On 5/1/24 14:23, Clément Chigot wrote: > > On Fri, Jan 5, 2024 at 12:32 PM Philippe Mathieu-Daudé > > wrote: > >> > >> Hi Clément, > >> > >> On 5/1/24 11:24, Clément Chigot

Re: [PATCH 3/9] intc/grlib_irqmp: implements the multiprocessor status register

On Fri, Jan 5, 2024 at 12:32 PM Philippe Mathieu-Daudé wrote: > > Hi Clément, > > On 5/1/24 11:24, Clément Chigot wrote: > > This implements the multiprocessor status register in grlib-irqmp and bind > > it to a start signal, which will be later wired in leon3-ge

Re: [PATCH 9/9] MAINTAINERS: replace Fabien by myself as Leon3 maintainer

On Fri, Jan 5, 2024 at 11:24 AM Clément Chigot wrote: > > CC: Fabien Chouteau Typo here... Should have been chout...@adacore.com... I'll update it in v2 if one is needed. Otherwise, could the one pushing these patches make the change for me ? Thanks and sorry for that. > Signed-o

[PATCH 5/9] target/sparc: implement asr17 feature for smp

This allows the guest program to know its cpu id. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- target/sparc/helper.c| 16 target/sparc/helper.h| 1 + target/sparc/translate.c | 13 +++-- 3 files changed, 20 insertions(+), 10 deletions

[PATCH 7/9] leon3: implement multiprocessor

This allows to register more than one CPU on the leon3_generic machine. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/sparc/leon3.c | 106 +-- 1 file changed, 74 insertions(+), 32 deletions(-) diff --git a/hw/sparc/leon3.c b

[PATCH 2/9] intc/grlib_irqmp: add ncpus property

This adds a "ncpus" property to the "grlib-irqmp" device to be used later, this required a little refactoring of how we initialize the device (ie: use realize instead of init). Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/int

[PATCH 0/9] sparc/leon3: Add support for -smp

/-/pipelines/1127834623. Clément Chigot (9): sparc/grlib: split out the headers for each peripherals intc/grlib_irqmp: add ncpus property intc/grlib_irqmp: implements the multiprocessor status register intc/grlib_irqmp: implements multicore irq target/sparc: implement asr17 feature for smp

[PATCH 3/9] intc/grlib_irqmp: implements the multiprocessor status register

This implements the multiprocessor status register in grlib-irqmp and bind it to a start signal, which will be later wired in leon3-generic to start a cpu. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/intc/grlib_irqmp.c | 22 +++--- 1 file changed, 19

[PATCH 1/9] sparc/grlib: split out the headers for each peripherals

... and move them in their right hardware directory. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/char/grlib_apbuart.c | 4 +-- hw/intc/grlib_irqmp.c | 4 +-- hw/sparc/leon3.c | 6 ++-- hw

[PATCH 9/9] MAINTAINERS: replace Fabien by myself as Leon3 maintainer

CC: Fabien Chouteau Signed-off-by: Clément Chigot --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 395f26ba86..a065e0b21f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1694,7 +1694,7 @@ F: hw/rtc/sun4v-rtc.c F: include/hw/rtc

[PATCH 6/9] target/sparc: simplify qemu_irq_ack

This is a simple cleanup, since env is passed to qemu_irq_ack it can be accessed from inside qemu_irq_ack. Just drop this parameter. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/sparc/leon3.c| 8 target/sparc/cpu.h | 2 +- target/sparc

[PATCH 4/9] intc/grlib_irqmp: implements multicore irq

Now there is an ncpus property, use it in order to deliver the IRQ to multiple CPU. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/intc/grlib_irqmp.c | 43 ++- hw/sparc/leon3.c | 3 ++- include/hw/intc/grlib_irqmp.h

[PATCH 8/9] leon3: check cpu_id in the tiny bootloader

Now that SMP is possible, the asr17 must be checked in the little boot code or the secondary CPU will reinitialize the Timer and the Uart. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot --- hw/sparc/leon3.c | 22 -- 1 file changed, 20 insertions(+), 2

Re: [PATCH for-8.2] accel/tcg: Remove CF_LAST_IO

Tested-by: Clément Chigot On Fri, Nov 10, 2023 at 6:08 PM Richard Henderson wrote: > > In cpu_exec_step_atomic, we did not set CF_LAST_IO, which can > lead to a loop with cpu_io_recompile. > > But since 18a536f1f8 ("Always require can_do_io") we no longer need > a fl

[PATCH v2] target/riscv: don't verify ISA compatibility for zicntr and zihpm

). riscv_cpu_disable_priv_spec_isa_exts was not updated when the above behavior was introduced, resulting in these extensions to be disabled after all. Signed-off-by: Clément Chigot Fixes: c004099330 ("target/riscv: add zicntr extension flag for TCG") Fixes: 0824121660 ("target/riscv: add zihpm extensi

[PATCH] target/riscv: don't verify ISA compatibility for zicntr and zihpm

). riscv_cpu_disable_priv_spec_isa_exts was not updated when the above behavior was introduced, resulting in these extensions to be disabled after all. Signed-off-by: Clément Chigot --- target/riscv/tcg/tcg-cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg

Re: [PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support

Hi Daniel, This series is triggering warnings when instantiating a CPU having a spec version older than 1.12. | $ qemu-system-riscv32 -M sifive_e | qemu-system-riscv32: warning: disabling zicntr extension for hart 0x because privilege spec version does not match | qemu-system-riscv32

Re: [PATCH 6/6] accel/tcg: Always require can_do_io

On Thu, Oct 26, 2023 at 2:44 AM Richard Henderson wrote: > > On 10/24/23 02:50, Clément Chigot wrote: > > Hi Richard, > > > > This commit has broken some of our internal bareboard testing on > > Risc-V 64. At some point in our programs, there is an AMOSWAP (= >

Re: [PATCH 6/6] accel/tcg: Always require can_do_io

Hi Richard, This commit has broken some of our internal bareboard testing on Risc-V 64. At some point in our programs, there is an AMOSWAP (= atomic swap) instruction on I/O. But since this commit, can_do_io is set to false triggering an infinite loop. IIUC the doc (cf [1]), atomic operations on I

[PATCH v4 2/5] softmmu: pass the main loop status to gdb "Wxx" packet

st be transfered to gdb as well. Signed-off-by: Clément Chigot Reviewed-by: Alistair Francis --- include/sysemu/sysemu.h | 2 +- softmmu/main.c | 2 +- softmmu/runstate.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/sysemu/sysemu.h b/include/sysemu/sys

[PATCH v4 0/5] Risc-V/gdb: replace exit calls with proper shutdown

sent before exiting. However, some features (see net/vhost-vdpa.c: vhost_vdpa_cleanup for example) are expecting that a cleanup is being made before exiting. This, it's probably safer to follow the same logic here as well. Difference with v3: - Rebase on riscv-to-apply Clément Chigot (5): soft

[PATCH v4 5/5] gdbstub: replace exit calls with proper shutdown for softmmu

This replaces the exit calls by shutdown requests, ensuring a proper cleanup of Qemu. Features like net/vhost-vdpa.c are expecting qemu_cleanup to be called to remove their last residuals. Signed-off-by: Clément Chigot Reviewed-by: Alistair Francis --- gdbstub/gdbstub.c | 5

[PATCH v4 3/5] hw/misc/sifive_test.c: replace exit calls with proper shutdown

ts after a shutdown request. Signed-off-by: Clément Chigot Reviewed-by: Alistair Francis --- hw/misc/sifive_test.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c index 56df45bfe5..ad688079c4 100644 --- a/hw/misc/sifive_test.

[PATCH v4 4/5] hw/char: riscv_htif: replace exit calls with proper shutdown

ts after a shutdown request. Signed-off-by: Clément Chigot Reviewed-by: Alistair Francis --- hw/char/riscv_htif.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 40de6b8b77..9bef60def1 100644 --- a/hw/char/riscv_htif.c +++

[PATCH v4 1/5] softmmu: add means to pass an exit code when requesting a shutdown

As of now, the exit code was either EXIT_FAILURE when a panic shutdown was requested or EXIT_SUCCESS otherwise. However, some hardware could want to pass more complex exit codes. Thus, introduce a new shutdown request function allowing that. Signed-off-by: Clément Chigot Reviewed-by: Alistair

Re: [PATCH v3 4/5] hw/char: riscv_htif: replace exit calls with proper shutdown

On Fri, Sep 22, 2023 at 7:20 AM Alistair Francis wrote: > > On Thu, Sep 7, 2023 at 9:26 PM Clément Chigot wrote: > > > > This replaces the exit calls by shutdown requests, ensuring a proper > > cleanup of Qemu. Otherwise, some connections like gdb could be broken >

Re: [PATCH v2 3/3] gdbstub: replace exit(0) with proper shutdown

Hi Peter, On Mon, Sep 4, 2023 at 2:46 PM Clément Chigot wrote: > > On Mon, Sep 4, 2023 at 11:42 AM Peter Maydell > wrote: > > > > On Mon, 4 Sept 2023 at 10:36, Clément Chigot wrote: > > > > > > On Mon, Sep 4, 2023 at 11:23 AM Peter Maydell > > &g

[PATCH v3 5/5] gdbstub: replace exit calls with proper shutdown for softmmu

This replaces the exit calls by shutdown requests, ensuring a proper cleanup of Qemu. Features like net/vhost-vdpa.c are expecting qemu_cleanup to be called to remove their last residuals. Signed-off-by: Clément Chigot --- gdbstub/gdbstub.c | 5 +++-- gdbstub/softmmu.c | 6

[PATCH v3 0/5] Risc-V/gdb: replace exit calls with proper shutdown

ith v2: - Add support to request a shutdown with a specific exit code. - Pass the exit code of the main loop to gdb_exit call in qemu_cleanup - gdbstub: move the request shutdown in a new new function to avoid having to worry about the request having already been sent. Clément Chigot (5): soft

[PATCH v3 4/5] hw/char: riscv_htif: replace exit calls with proper shutdown

ts after a shutdown request. Signed-off-by: Clément Chigot --- hw/char/riscv_htif.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 37d3ccc76b..7e9b6fcc98 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -

[PATCH v3 3/5] hw/misc/sifive_test.c: replace exit calls with proper shutdown

ts after a shutdown request. Signed-off-by: Clément Chigot --- hw/misc/sifive_test.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c index 56df45bfe5..ad688079c4 100644 --- a/hw/misc/sifive_test.c +++ b/hw/misc/sifive_test.c @@ -

[PATCH v3 1/5] softmmu: add means to pass an exit code when requesting a shutdown

As of now, the exit code was either EXIT_FAILURE when a panic shutdown was requested or EXIT_SUCCESS otherwise. However, some hardware could want to pass more complex exit codes. Thus, introduce a new shutdown request function allowing that. Signed-off-by: Clément Chigot --- include/sysemu

[PATCH v3 2/5] softmmu: pass the main loop status to gdb "Wxx" packet

st be transfered to gdb as well. Signed-off-by: Clément Chigot --- include/sysemu/sysemu.h | 2 +- softmmu/main.c | 2 +- softmmu/runstate.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index 25be2a692e..73a37

Re: [PATCH v2 3/3] gdbstub: replace exit(0) with proper shutdown

On Mon, Sep 4, 2023 at 11:42 AM Peter Maydell wrote: > > On Mon, 4 Sept 2023 at 10:36, Clément Chigot wrote: > > > > On Mon, Sep 4, 2023 at 11:23 AM Peter Maydell > > wrote: > > > > > > On Wed, 23 Aug 2023 at 08:07, Clément Chigot wrote: > >

Re: [PATCH v2 3/3] gdbstub: replace exit(0) with proper shutdown

On Mon, Sep 4, 2023 at 11:23 AM Peter Maydell wrote: > > On Wed, 23 Aug 2023 at 08:07, Clément Chigot wrote: > > > > This replaces the exit(0) call by a shutdown request, ensuring a proper > > cleanup of Qemu. Otherwise, some connections could be broken without >

[PATCH v2 3/3] gdbstub: replace exit(0) with proper shutdown

This replaces the exit(0) call by a shutdown request, ensuring a proper cleanup of Qemu. Otherwise, some connections could be broken without being correctly flushed. Signed-off-by: Clément Chigot --- gdbstub/gdbstub.c | 3 +-- gdbstub/softmmu.c | 13 + gdbstub/user.c| 2 ++ 3

[PATCH v2 1/3] hw/misc/sifive_test.c: replace exit(0) with proper shutdown

This replaces the exit(0) call by a shutdown request, ensuring a proper cleanup of Qemu. Otherwise, some connections like gdb could be broken without being correctly flushed. Signed-off-by: Clément Chigot Reviewed-by: Alistair Francis --- hw/misc/sifive_test.c | 4 +++- 1 file changed, 3

[PATCH v2 2/3] hw/char: riscv_htif: replace exit(0) with proper shutdown

This replaces the exit(0) call by a shutdown request, ensuring a proper cleanup of Qemu. Otherwise, some connections like gdb could be broken without being correctly flushed. Signed-off-by: Clément Chigot Reviewed-by: Alistair Francis --- hw/char/riscv_htif.c | 12 +++- 1 file changed

[PATCH v2 0/3] Risc-V/gdb: replace exit(0) with proper shutdown

low to pass the exit code, only perform the above modification on a sucessful exit. Difference with v1: - avoid sending a shutdown request in gdb_exit if one has already been set. Clément Chigot (3): hw/misc/sifive_test.c: replace exit(0) with proper shutdown hw/char: riscv_htif: repla

Re: [PATCH 3/3] gdbstub: replace exit(0) with proper shutdown

On Fri, Aug 18, 2023 at 11:10 AM Peter Maydell wrote: > > On Fri, 18 Aug 2023 at 10:03, Clément Chigot wrote: > > > > This replaces the exit(0) call by a shutdown request, ensuring a proper > > cleanup of Qemu. Otherwise, some connections could be broken without >

[PATCH 3/3] gdbstub: replace exit(0) with proper shutdown

This replaces the exit(0) call by a shutdown request, ensuring a proper cleanup of Qemu. Otherwise, some connections could be broken without being correctly flushed. Signed-off-by: Clément Chigot --- gdbstub/gdbstub.c | 3 +-- gdbstub/softmmu.c | 11 +++ gdbstub/user.c| 2 ++ 3

[PATCH 2/3] hw/char: riscv_htif: replace exit(0) with proper shutdown

This replaces the exit(0) call by a shutdown request, ensuring a proper cleanup of Qemu. Otherwise, some connections like gdb could be broken without being correctly flushed. Signed-off-by: Clément Chigot --- hw/char/riscv_htif.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion

[PATCH 1/3] hw/misc/sifive_test.c: replace exit(0) with proper shutdown

This replaces the exit(0) call by a shutdown request, ensuring a proper cleanup of Qemu. Otherwise, some connections like gdb could be broken without being correctly flushed. Signed-off-by: Clément Chigot --- hw/misc/sifive_test.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff

[PATCH 0/3] Risc-V/gdb: replace exit(0) with proper shutdown

t allow to pass the exit code, only perform the above modification on a sucessful exit. Clément Chigot (3): hw/misc/sifive_test.c: replace exit(0) with proper shutdown hw/char: riscv_htif: replace exit(0) with proper shutdown gdbstub: replace exit(0) with proper shutdown gdbstub/gdb

Re: [PATCH] hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number

On Wed, May 24, 2023 at 5:06 PM Philippe Mathieu-Daudé wrote: > > Hi Clément, > > On 24/5/23 16:37, Clément Chigot wrote: > > When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS, > > the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result

[PATCH] hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number

l RPUs. | $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102 | ** | ERROR:../src/tcg/tcg.c:777:tcg_register_thread: | assertion failed: (n < tcg_max_ctxs) Signed-off-by: Clément Chigot --- hw/arm/xlnx-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/xlnx-z

Re: [PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

t_priority[addrid] = value % > +(plic->num_priorities + 1); > +sifive_plic_update(plic); > +} else if (value <= plic->num_priorities) { > plic->target_priority[addrid] = value; > sifive_plic_update(plic); > } > -- > 2.17.1 Reviewed-by: Clément Chigot

Re: [PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

Hi Jim, On Fri, Sep 30, 2022 at 2:32 PM Jim Shu wrote: > > PLIC spec [1] requires interrupt source priority registers are WARL > field and the number of supported priority is power-of-2 to simplify SW > discovery. > > Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC > spec,

Re: [PATCH] hw/intc: sifive_plic: fix hard-coded max priority level

Hi Jim, On Sun, Sep 25, 2022 at 3:26 PM Jim Shu wrote: > > The maximum priority level is hard-coded when writing to interrupt > priority register. However, when writing to priority threshold register, > the maximum priority level is from num_priorities Property which is > configured by platform.

[PATCH] target/arm: Fix alignment for VLD4.32

When requested, the alignment for VLD4.32 is 8 and not 16. See ARM documentation about VLD4 encoding: ebytes = 1 << UInt(size); if size == '10' then alignment = if a == '0' then 1 else 8; else alignment = if a == '0' then 1 else 4*eb

Re: Question about loading bare metal firmware

> > Hi all, > > > > I'm wondering if there is an official way to load bare metal software > > within qemu emulations. > > I've seen a lot of people (including us) using -kernel. However, the > > doc seems to imply that the generic loader would be a better approach > > (cf [1]). I know that the comp

Question about loading bare metal firmware

Hi all, I'm wondering if there is an official way to load bare metal software within qemu emulations. I've seen a lot of people (including us) using -kernel. However, the doc seems to imply that the generic loader would be a better approach (cf [1]). I know that the compatibility with older Qemus

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