RE: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type

2020-04-24 Thread Corey Wharton
> -Original Message- > From: Alistair Francis > Sent: Friday, April 24, 2020 9:04 AM > To: Corey Wharton > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Sagar Karandikar > ; Bastian Koppelmann paderborn.de>; Alistair Francis ; Palmer Dabbelt >

Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine

2020-04-06 Thread Corey Wharton
ping https://patchwork.kernel.org/patch/11437661/ https://patchwork.kernel.org/patch/11437665/ From: Corey Wharton Sent: Friday, March 13, 2020 12:35 PM To: qemu-devel@nongnu.org ; qemu-ri...@nongnu.org Cc: Palmer Dabbelt ; Alistair Francis ; Sagar Karandikar

[PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type

2020-03-13 Thread Corey Wharton
The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton --- v2: Added missing RVU flag target/riscv/cpu.c | 10 ++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target

[PATCH v2 0/2] Support different CPU types for the sifive_e machine

2020-03-13 Thread Corey Wharton
extension (f). The default CPU for the sifive_e machine is unchanged. v2: Added missing RVU flag Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type hw/riscv/sifive_e.c | 3 ++- target/riscv/cpu.c | 10 ++ target/riscv/cpu.h | 1 + 3

[PATCH v2 1/2] riscv: sifive_e: Support changing CPU type

2020-03-13 Thread Corey Wharton
Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv

[PATCH 2/2] target/riscv: Add a sifive-e34 cpu type

2020-03-12 Thread Corey Wharton
The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton --- target/riscv/cpu.c | 10 ++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH 1/2] riscv: sifive_e: Support changing CPU type

2020-03-12 Thread Corey Wharton
Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton --- hw/riscv/sifive_e.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a254cad489..b0a611adb9 100644 --- a/hw/riscv

[PATCH 0/2] Support different CPU types for the sifive_e machine

2020-03-12 Thread Corey Wharton
extension (f). The default CPU for the sifive_e machine is unchanged. A user can change the default CPU type by specifying it with the '-cpu' option on the command line. Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type hw/riscv/sifiv

[PATCH 1/2] riscv: sifive_e: Support changing CPU type

2020-03-12 Thread Corey Wharton
Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton --- hw/riscv/sifive_e.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a254cad489..b0a611adb9 100644 --- a/hw/riscv

[PATCH 0/2] Support different CPU types for the sifive_e machine

2020-03-12 Thread Corey Wharton
extension (f). The default CPU for the sifive_e machine is unchanged. A user can change the default CPU type by specifying it with the '-cpu' option on the command line. Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type hw/riscv/sifiv

[PATCH 2/2] target/riscv: Add a sifive-e34 cpu type

2020-03-12 Thread Corey Wharton
The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton --- target/riscv/cpu.c | 10 ++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv