be to perform a write on the second step rather than just
a reservation.
But aside from that the problem remains the same and the patch does
solve it.
On Oct 6, 2011, at 10:05 AM, Alexander Graf wrote:
From: Elie Richa ri...@adacore.com
In the current emulation of the load-and-reserve (lwarx
The flexible array member should remain the last member in the structure
as this assumption is based upon in the code.
Signed-off-by: Elie Richa ri...@adacore.com
---
slirp/mbuf.h |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/slirp/mbuf.h b/slirp/mbuf.h
index
Hello,
I've had this problem recently and your patch does fix the issue, thanks!
Regards,
Elie
On 08/10/2011 01:41 PM, Sebastian Bauer wrote:
When using gdb to single step a ppc interrupt routine, the execution flow passes
the rfi instruction without actually returning from the interrupt. The
board if needed.
Even though my patch is rather harsh, it has the advantage of solving
the problem for any number of CPUs without touching the translation
code. And it does not affect normal execution as I explained in the
previous mail.
Regards,
Elie
On 07/22/2011 05:58 PM, Elie Richa wrote
On 07/23/2011 12:49 PM, Alexander Graf wrote:
@@ -1304,6 +1304,10 @@ static void mpic_reset (void *opaque)
mpp-src[i].ipvp = 0x8080;
mpp-src[i].ide = 0x0001;
}
+/* Set IDE for IPIs to 0 so we don't get spurious interrupts */
+for (i = mpp-irq_ipi0; i
Hello.
I have been working on SMP support for the MPC8641D processor, so I have also
worked on completing the SMP implementation of MPIC. I've been meaning to post a
patch, but you beat me to it :)
I compared your implementation to mine, and it boils down to the same, except
that I had
On 07/21/2011 03:27 AM, Alexander Graf wrote:
@@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque)
mpp-glbc = 0x8000;
/* Initialise controller registers */
-mpp-frep = 0x004f0002;
+mpp-frep = 0x004f0002 | ((MAX_CPU - 1) 8);
Should we really report the maximum
before a CPU switch occurs. However in the rare case
where a CPU switch does occur between the lwarx and its corresponding
stwcx. this patch solves a potential erroneous behavior of the
synchronization instructions.
Signed-off-by: Elie Richa ri...@adacore.com
---
cpu-exec.c |1 +
1 files
