Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation

On 5/24/2024 1:39 AM, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf

Re: [PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h

On 5/24/2024 1:39 AM, Daniel Henrique Barboza wrote: ... +/* 5.4 Features control register (32bits) */ +#define RISCV_IOMMU_REG_FCTL0x0008 Looks like doesn't support RISCV_IOMMU_FCTL_BE? If so, need to implement it as read-only? along with other 2 bits. IIUC, diff --git a/hw/riscv

Re: [PATCH v2 02/15] hw/riscv: add riscv-iommu-bits.h

On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote: From: Tomasz Jeznach This header will be used by the RISC-V IOMMU emulation to be added in the next patch. Due to its size it's being sent in separate for an easier review. One thing to notice is that this header can be replaced by the futur

Re: [PATCH v2 06/15] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote: From: Tomasz Jeznach Generate device tree entry for riscv-iommu PCI device, along with mapping all PCI device identifiers to the single IOMMU device instance. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza --- hw/ri