Dear Maintainers and Paolo,
I hope this email finds you well. This is my second follow-up regarding the
patch I submitted for review. I previously sent a reminder on July 23rd, but
I have yet to receive any updates or further comments.
I understand that you have many responsibilities, but I would
ssumes
Hyper-Threading is not supported. For Intel and similar vCPUs, if the
CMPLegacy bit is not masked in CPUID[0x8001].ECX, Linux will incorrectly
assume that Hyper-Threading is not supported, even if the vCPU does support it.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai
Review
in
QEMU, making this change straightforward.
Additionally, the IS_ZHAOXIN_CPU macro has been added to simplify the
checks for Zhaoxin CPUs.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a
ely reflecting their functionality
and performance characteristics.
### Summary of changes
EwanHai (4):
target/i386: Add support for Zhaoxin CPU vendor identification
target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
target/i386: Introduce Zhaoxin Yongfeng CPU model
target/i386: Mask CM
Add new CPUID feature flags for various Zhaoxin PadLock extensions.
These definitions will be used for Zhaoxin CPU models.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386/cpu.h b/target
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai
Review
supported. For Intel
and similar vCPUs, if the CMPLegacy bit is not masked in CPUID[0x8001].ECX,
Linux will incorrectly assume that Hyper-Threading is not supported, even if
the vCPU does support it.
Signed-off-by: EwanHai
---
target/i386/cpu.c | 7 +++
1 file changed, 3 insertions(+), 4 d
ely reflecting their functionality
and performance characteristics.
### Summary of changes
EwanHai (4):
target/i386: Add support for Zhaoxin CPU vendor identification
target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
target/i386: Introduce Zhaoxin Yongfeng CPU model
target/i386: Mask CM
in
QEMU, making this change straightforward.
Additionally, the IS_ZHAOXIN_CPU macro has been added to simplify the
checks for Zhaoxin CPUs.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a
Add new CPUID feature flags for various Zhaoxin PadLock extensions.
These definitions will be used for Zhaoxin CPU models.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386/cpu.h b/target
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai
---
t
### Summary of changes
EwanHai (4):
target/i386: Add support for Zhaoxin CPU vendor identification
target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
target/i386: Introduce Zhaoxin Yongfeng CPU model
target/i386: Update CMPLegacy handling for Zhaoxin CPUs
target/i386/cpu.c | 128
Zhaoxin CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
vendor to align their behavior with Intel.
Signed-off-by: EwanHai
---
target/i386/cpu.c | 4 +---
1 file changed, 1
in
QEMU, making this change straightforward.
Additionally, the IS_ZHAOXIN_CPU macro has been added to simplify the
checks for Zhaoxin CPUs.
Signed-off-by: EwanHai
---
target/i386/cpu.h | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/tar
Add new CPUID feature flags for various Zhaoxin PadLock extensions.
These definitions will be used for Zhaoxin CPU models.
Signed-off-by: EwanHai
---
target/i386/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior with Intel.
Signed-off-by: EwanHai
---
target/i386/cpu.c | 6 +++---
1 file
This patch adds CPUID vendor strings and macros to identify Zhaoxin/VIA CPUs.
Changes:
- Added Zhaoxin/VIA CPUID vendor strings.
- Defined CPUID_VENDOR_ZHAOXIN.
- Added IS_ZHAOXIN_CPU/IS_VIA_CPU macro.
Signed-off-by: EwanHai
---
target/i386/cpu.h | 17 +
1 file changed, 17
Add new CPUID feature flags for various VIA PadLock extensions.
These definitions will be used for ZHAOXIN/VIA CPU models.
Signed-off-by: EwanHai
---
target/i386/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai
---
t
.
### Summary of Changes
EwanHai (4):
target/i386: Add support for Zhaoxin/VIA CPU vendor identification
target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
target/i386: Introduce Zhaoxin Yongfeng CPU model
target/i386: Update CMPLegacy handling for Zhaoxin and VIA CPUs
target/i386/cpu.c
he value of
this MSR.
This patch supplements the above logic, ensuring that
`has_msr_vmx_procbased_clts2` is correctly set by checking both MSR
lists, thus maintaining compatibility with older kernels.
Signed-off-by: EwanHai
---
Changes in v3:
- Use a more precise version range in the comment, sp
alue of this MSR.
This patch supplements the above logic, ensuring that
`has_msr_vmx_procbased_clts2` is correctly set by checking both MSR
lists, thus maintaining compatibility with older kernels.
Signed-off-by: EwanHai
---
In response to the suggestions from ZhaoLiu(zhao1@intel.com),
the foll
/lore.kernel.org/all/20230925071453.14908-1-ewanhai...@zhaoxin.com/.
I've double-checked to ensure I CC'd the relevant maintainers and addressed
previous review comments, if any. I understand that everyone is busy and some
patches might get overlooked, especially in less-maintained areas.
ns the value of this MSR.
This patch supplements the above logic, ensuring that
`has_msr_vmx_procbased_clts2` is correctly set by checking both MSR
lists, thus maintaining compatibility with older kernels.
Signed-off-by: EwanHai
---
target/i386/kvm/kvm.c | 6 ++
1 file changed, 6 insertions(+
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