On Mon, 22 Nov 2021, Peter Maydell wrote:
> On Sat, 20 Nov 2021 at 23:40, Finn Thain wrote:
> > Anyway, thanks for taking the time to write. A competent reviewer has to
> > do much more than that, but I'm not paying for competence so I suppose I'm
> > asking too
On Sat, 20 Nov 2021, Mark Cave-Ayland wrote:
> On 19/11/2021 08:39, Finn Thain wrote:
>
> > On Thu, 18 Nov 2021, Mark Cave-Ayland wrote:
> >
> >>
> >> Hi Finn,
> >>
> >> I've not forgotten about this series - we're now in
On Thu, 18 Nov 2021, Mark Cave-Ayland wrote:
>
> Hi Finn,
>
> I've not forgotten about this series - we're now in 6.2 freeze, but it's
> on my TODO list to revisit in the next development cycle this along with
> the ESP stress-ng changes which I've also been looking at. As mentioned
> in my p
VIA1 timer. This approach should help mitigate the clock drift
> problem as well as assist with CONFIG_GENERIC_CLOCKEVENTS adoption,
> which would enable CONFIG_NO_HZ_IDLE etc.
>
> [2] https://github.com/mcayland/qemu/commits/q800.upstream
>
> [3] https://github.com/fthain/qemu/
Signed-off-by: Finn Thain
---
Changed since RFC:
- Improved code commentary and commit log text.
- Removed qemu_clock_get_ns() call from set_counter() for simplicity.
- Moved the changes to the QEMUTimer callbacks from the previous patch
into this one because they relate more to syncronizati
Timer 1 has two modes: continuous interrupt and oneshot.
Signed-off-by: Finn Thain
---
Changed since RFC:
- Moved to end of series. This patch is quite a bit shorter here.
---
hw/misc/mos6522.c | 6 --
include/hw/misc/mos6522.h | 2 ++
2 files changed, 6 insertions(+), 2 deletions
It necessary to call mos6522_update_irq() when the interrupt flags
change and unnecessary when they haven't.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
---
hw/misc/mos6522.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mos6522.c b/hw
mos6522_read() and mos6522_write() may call various functions to determine
timer irq state, timer counter value and QEMUTimer deadline. All called
functions must use the same value for the present time.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
---
Changed since RFC
- Moved
rter than 20 ms.
---
Changed since RFC:
- Added Reviewed-by tags.
- Re-ordered some patches to make fixes available earlier in the series.
- Dropped patch 5/10 "Don't clear T1 interrupt flag on latch write".
- Rebased on v6.1.0 release.
Finn Thain (9):
hw/mos6522: Remove get_lo
This improves readability.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
---
hw/misc/mos6522.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 1d4a56077e..c0d6bee4cc 100644
--- a/hw/misc/mos6522.c
+++ b
This code appears to be unnecessary.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
---
hw/misc/mos6522.c | 22 ++
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index a478c1ca43..ff246b5437 100644
--- a
reloaded when it wraps.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index c0d6bee4cc..6bd60f2118 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -63,15 +63,16
Reads and writes to the TL and TC registers have no immediate effect on
a running timer, with the exception of a write to TCH. Hence these
mos6522_timer_update() calls are not needed.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/hw
This code appears to be unnecessary.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
---
hw/misc/mos6522.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 1c57332b40..a478c1ca43 100644
--- a/hw
On Fri, 10 Sep 2021, Mark Cave-Ayland wrote:
> On 01/09/2021 09:06, Mark Cave-Ayland wrote:
>
> > I'll have a go at some basic timer measurements using your patch to
> > see what sort of numbers I get for the latency here. Obviously QEMU
> > doesn't guarantee response times but over 20ms does s
On Wed, 1 Sep 2021, Laurent Vivier wrote:
> Le 26/08/2021 à 07:21, Finn Thain a écrit :
> > On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> >
> >> On 24/08/2021 11:09, Finn Thain wrote:
> >>
> >>> The Synertek datasheet says, "A write to T1L-H
On Tue, 31 Aug 2021, Mark Cave-Ayland wrote:
> You mentioned that the OS may compensate for the fact that the 6522
> doesn't have an overflow flag: can you explain more as to how this works
> in Linux?
When running on real hardware, Linux/mac68k does so by
- Elevating the interrupt priority o
On Tue, 31 Aug 2021, Mark Cave-Ayland wrote:
> On 28/08/2021 02:22, Finn Thain wrote:
>
> > > On 8/24/21 12:09 PM, Finn Thain wrote:
> > >
> > > > On a real Quadra, accesses to the SY6522 chips are slow because they are
> > > > synchronous with
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > mos6522_read() and mos6522_write() may call various functions to determine
> > timer irq state, timer counter value and QEMUTimer deadline. All called
> > functions must use the sa
On Tue, 24 Aug 2021, Philippe Mathieu-Daudé wrote:
> On 8/24/21 12:09 PM, Finn Thain wrote:
> > mos6522_read() and mos6522_write() may call various functions to determine
> > timer irq state, timer counter value and QEMUTimer deadline. All called
> > functions must use t
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > Signed-off-by: Finn Thain
> > ---
> > hw/misc/mos6522.c | 19 ---
> > include/hw/misc/mos6522.h | 3 +++
> > 2 files changed, 15 inserti
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > This is a patch series that I started last year. The aim was to try to
> > get a monotonic clocksource for Linux/m68k guests. That aim hasn't been
> > achieved yet (for q800
On Tue, 24 Aug 2021, Philippe Mathieu-Daudé wrote:
> On 8/24/21 12:09 PM, Finn Thain wrote:
>
> > On a real Quadra, accesses to the SY6522 chips are slow because they are
> > synchronous with the 783360 Hz "phase 2" clock. In QEMU, they are slow
> > only be
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > This code appears to be unnecessary.
> >
> > Signed-off-by: Finn Thain
> > ---
> > hw/misc/mos6522.c | 22 +-
> > 1 file changed, 1 i
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > The first reload of timer 1 is early by half of a clock cycle as it gets
> > measured from a falling edge. By contrast, the succeeding reloads are
> > measured from ri
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
>
> Unfortunately the datasheet I was using for reference doesn't appear to
> have the relevant detail here. Have you got a reference to the datasheet
> you're using which shows what happens to the timers at the zero crossing
> point?
>
The data
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > The Synertek datasheet says, "A write to T1L-H loads an 8-bit count value
> > into the latch. A read of T1L-H transfers the contents of the latch to
> > the data bus. Neither
get_counter() may need to use the old latch value in order to
reload the counter.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 154 --
hw/misc/trace-events | 2 +-
include/hw/misc/mos6522.h | 8 +-
3 files changed, 88 insertions(+), 76
It necessary to call mos6522_update_irq() when the interrupt flags
change and unnecessary when they haven't.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 0a241fe9f8..0dd3c
mos6522_read() and mos6522_write() may call various functions to determine
timer irq state, timer counter value and QEMUTimer deadline. All called
functions must use the same value for the present time.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 51
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 19 ---
include/hw/misc/mos6522.h | 3 +++
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 8991f4..5b1657ac0d 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc
reloaded when it wraps.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 5b1657ac0d..0a241fe9f8 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -63,15 +63,16
Reads and writes to the TL and TC registers have no immediate effect on
a running timer, with the exception of a write to TCH. Hence these
mos6522_timer_update() calls are not needed.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/hw
The Synertek datasheet says, "A write to T1L-H loads an 8-bit count value
into the latch. A read of T1L-H transfers the contents of the latch to
the data bus. Neither operation has an affect [sic] on the interrupt
flag."
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 1 -
1 file
This improves readability.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 1d4a56077e..c0d6bee4cc 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -154,7 +154,7
This code appears to be unnecessary.
Also, these routines don't return the counter value but a time interval
between counter values, so they are misnamed.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 22 ++
1 file changed, 2 insertions(+), 20 deletions(-)
diff --
This code appears to be unnecessary.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 1c57332b40..a478c1ca43 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522
/github.com/fthain/qemu/commits/via-timer/
[4] This theoretical 20 ms deadline is not missed prior to every
backwards jump in the clocksource counter. AFAICT, that's because the
true deadline is somewhat shorter than 20 ms.
Finn Thain (10):
hw/mos6522: Remove get_load_time() me
On Mon, 12 Jul 2021, Finn Thain wrote:
> On Sun, 11 Jul 2021, Philippe Mathieu-Daudé wrote:
>
> >
> > > If I'm right that the big_endian flag should go away, commit
> > > b1600ff195 ("hw/mips/jazz: specify correct endian for dp8393x
> > >
On Sun, 11 Jul 2021, Philippe Mathieu-Daudé wrote:
>
> > If I'm right that the big_endian flag should go away, commit
> > b1600ff195 ("hw/mips/jazz: specify correct endian for dp8393x device")
> > has already taken mainline in the wrong direction and amounts to
> > churn.
>
> We might figure
builds worked fine with my NetBSD/arc, Linux/mipsel and Linux/m68k guests.
Tested-by: Finn Thain
I have no objection to patch 8/8 ("dp8393x: don't force 32-bit register
access"). I asked Mark to explain why it was a bug fix (since it didn't
change QEMU behaviour in my test
On Wed, 7 Jul 2021, Mark Cave-Ayland wrote:
> > You don't need a rootfs to see the jazzsonic driver messages. But if
> > you still want one, you could try the mipsel builds from these distros
> > (not the 64-bit ones):
> >
> > https://ftp.jaist.ac.jp/pub/Linux/Gentoo/experimental/mips/stages/
On Wed, 7 Jul 2021, Mark Cave-Ayland wrote:
> However this conflicts with what you mention above that the SONIC is
> hard-coded into little-endian mode, in which case we would still need to
> keep it.
>
If you want to fully implement BMODE in QEMU then you'll need to abandon
native endiannes
On Mon, 5 Jul 2021, Mark Cave-Ayland wrote:
> On 05/07/2021 02:36, Finn Thain wrote:
>
> > > Unfortunately I don't have a test mips64el image available to see if
> > > this combination works for Linux. Phil, do you have a suitable test
> > > kernel and r
On Mon, 5 Jul 2021, Philippe Mathieu-Daudé wrote:
> On 7/5/21 2:58 AM, Finn Thain wrote:
> > On Mon, 5 Jul 2021, Philippe Mathieu-Daudé wrote:
> >
> >> Test NetBSD 5.1 on the Jazz Magnum machine. As the firmware is not
> >> redistributable, it has to be extrac
On Mon, 5 Jul 2021, Mark Cave-Ayland wrote:
> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" set
> .impl.min_access_size
> and .impl.max_access_size to 4 to try and fix the Linux jazzsonic driver
> which uses
> 32-bit accesses.
>
> The problem with forcing the register access to 32-bit
On Mon, 5 Jul 2021, Mark Cave-Ayland wrote:
> From: Philippe Mathieu-Daudé
>
> Per the DP83932C datasheet from July 1995:
>
> 4.0 SONIC Registers
> 4.1 THE CAM UNIT
>
> The Content Addressable Memory (CAM) consists of sixteen
> 48-bit entries for complete address filtering of netwo
On Sun, 4 Jul 2021, Mark Cave-Ayland wrote:
> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that all
> accesses
> to the registers were 32-bit
As I said, that assumption was not made there.
If commit 3fe9a838ec is deficient it is probably because I am unaware of
the ability
On Sun, 4 Jul 2021, Mark Cave-Ayland wrote:
> On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
>
> > Instead of accessing N registers via a single address_space API
> > call using a temporary buffer (stored in the device state) and
> > updating each register, move the address_space call in the
On Mon, 5 Jul 2021, Philippe Mathieu-Daudé wrote:
> Test NetBSD 5.1 on the Jazz Magnum machine. As the firmware is not
> redistributable, it has to be extracted from the floppy configuration
> disk coming with a Mips Magnum 4000 system, then the NTPROM_BIN_PATH
> environment variable has to be set
re 16-bit then we can simply set .impl.min_access to 2
> and
> then the memory API will automatically do the right thing for both 16-bit
> accesses
> used by Linux and 32-bit accesses used by the MacOS toolbox ROM.
>
> Signed-off-by: Mark Cave-Ayland
> Fixes: 3fe9a838ec (&
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> Instead of accessing N registers via a single address_space API
> call using a temporary buffer (stored in the device state) and
> updating each register, move the address_space call in the
> register put/get. The load/store and word size checks
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> Hi Mark, few more patches while reviewing.
>
>
>
> Again, not tested (yet)... Simply compiled.
>
>
>
> Please tell me what you think of them.
>
>
I think these 3 patches can be reduced to this theoretical bug fix:
diff --git a/hw/net/d
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> When the CRCI (CRC INHIBIT) bit is set, the 4-byte FCS field
> is not transmitted.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/dp8393x.c | 22 ++
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --g
On Thu, 1 Jul 2021, Philippe Mathieu-Daudé wrote:
> On 6/25/21 8:53 AM, Mark Cave-Ayland wrote:
> > Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that
> > all accesses to the registers were 32-bit
No, that assumption was not made there. Just take a look at my commits in
Linux
achine will have
> more breaking migration changes as further MacOS toolbox ROM support is
> upstreamed and b) the magnum machine migration is currently broken (and
> has been for quite some time).
>
> Signed-off-by: Mark Cave-Ayland
>
Tested-by: Finn Thain
My testing was m
On Fri, 25 Jun 2021, Mark Cave-Ayland wrote:
> On 25/06/2021 05:36, Finn Thain wrote:
>
> > On Thu, 24 Jun 2021, Mark Cave-Ayland wrote:
> >
> > > Thanks for the link and the detailed testing information. I've been
> > > trying to understand why
On Thu, 24 Jun 2021, Mark Cave-Ayland wrote:
> Thanks for the link and the detailed testing information. I've been
> trying to understand why you had to set the MAC address in the ARC
> firmware so I had a bit of an experiment here.
>
> The reason that you need to do this is because of the NVRA
Hi Mark,
On Wed, 16 Jun 2021, Mark Cave-Ayland wrote:
> On 16/06/2021 04:09, Finn Thain wrote:
>
> > With "qemu-system-mips -M magnum ..." I was able to boot both Linux
> > and NetBSD. That was after commit 89ae0ff9b7 ("net/dp8393x: add PROM
> > to sto
On Mon, 14 Jun 2021, Mark Cave-Ayland wrote:
> On 14/06/2021 06:36, Philippe Mathieu-Daudé wrote:
>
> > Cc'ing Finn & Laurent.
> >
> > On 6/13/21 6:37 PM, Mark Cave-Ayland wrote:
> > > Here is the next set of patches from my attempts to boot MacOS under
> > > QEMU's Q800 machine related to the
Signed-off-by: Finn Thain
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index a1bd659817..772f3e16cf 100644
--- a/.mailmap
+++ b/.mailmap
@@ -91,6 +91,7 @@ Erik Smit
Fabrice Desclaux
Fernando Luis Vázquez Cao
Fernando Luis Vázquez Cao
+Finn Thain
On Sat, 20 Jun 2020, Finn Thain wrote:
>
> Thanks for picking these fixes. When the maintainer originally merged this
> series of patches, the first patch got slightly damaged. This was remedied
> in a subsequent patch[1]. That is, mainline commit a0cf4297d6 ("dp8393x:
&g
Hi Michael,
On Tue, 16 Jun 2020, Michael Roth wrote:
>
> Finn Thain (14):
> dp8393x: Mask EOL bit from descriptor addresses
> dp8393x: Always use 32-bit accesses
> dp8393x: Clean up endianness hacks
> dp8393x: Have dp8393x_receive() return the packet si
Tested-by: Finn Thain
Thanks for all your work on this.
I've just noticed a discrepancy between the traces from an ADB bus scan on
Laurent's Apple Quadra and an ADB bus scan on your patched QEMU machine.
Apple Q800:
[C1f][s ][Rff-][Rff ][rff-]
[C2f][s ][R61 ][R05 ][r00
A portion of a recent patch got lost due to a merge snafu. That patch is
now commit 88f632fbb1 ("dp8393x: Mask EOL bit from descriptor addresses").
This patch restores the portion that got lost.
Signed-off-by: Finn Thain
---
hw/net/dp8393x.c | 4 ++--
1 file changed, 2 insert
ge conflicts
were resolved. The conflicts were apparently caused by commit 19f7034773
("Avoid address_space_rw() with a constant is_write argument").
Regards,
Finn
On Tue, 3 Mar 2020, Jason Wang wrote:
> From: Finn Thain
>
> The Least Significant bit of a descriptor addre
On Tue, 18 Feb 2020, Aleksandar Markovic wrote:
> On Wednesday, January 29, 2020, Finn Thain
> wrote:
>
> > Hi All,
> >
> > There are bugs in the emulated dp8393x device that can stop packet
> > reception in a Linux/m68k guest (q800 machine).
> >
> &
According to the datasheet, section 3.4.4, "in 32-bit mode ... the SONIC
always writes long words".
Therefore, use the same technique for the 'in_use' field that is used
everywhere else, and write the full long word.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
R
These operations need to take place regardless of whether or not
rx descriptors have been used up (that is, EOL flag was observed).
The algorithm is now the same for a packet that was withheld as for
a packet that was not.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
hw/net
word (16-bit mode) or long word (32-bit mode)
if the last byte did not end on a word or long word boundary
respectively. The fill byte will be 0FFh.
Implement buffer padding so that buffer limits are correctly enforced.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
Reviewed-by
Added 2 new patches.
Changed since v3:
- Replaced patch 13/14 with patch suggested by Philippe Mathieu-Daudé.
Finn Thain (14):
dp8393x: Mask EOL bit from descriptor addresses
dp8393x: Always use 32-bit accesses
dp8393x: Clean up endianness hacks
dp8393x: Have dp8393x_receive() retur
turns false. This bug causes the SONIC to become
deaf (until reset).
Fix this with a new flag to indicate actual receive buffer exhaustion.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
Changed since v2:
- Don't use can_receive to suspend packet reception.
- Don't misuse th
The Least Significant bit of a descriptor address register is used as
an EOL flag. It has to be masked when the register value is to be used
as an actual address for copying memory around. But when the registers
are to be updated the EOL bit should not be masked.
Signed-off-by: Finn Thain
Tested
them. Linux uses that interrupt to
count dropped packets.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
Changed since v1:
- Perform length check after Recieve Control Register initialization.
---
hw/net/dp8393x.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/net/dp83
quot;net/dp8393x: fix hardware reset")
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Finn Thain
---
Changed since v3:
- Simplified as per suggestion from Philippe Mathieu-Daudé.
---
hw/net/dp8393x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/dp8393x.c b/hw/
RXpkt.in_use field.
The packet can now be processed by the host, so raise a PKTRX interrupt,
just like the normal case.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
Changed since v2:
- Assert PKTRX interrupt when releasing withheld packet.
---
hw/net/dp8393x.c | 10 ++
1
Linux 'jazzsonic' driver working, and avoids the need for
prior hacks to make the NetBSD 'sn' driver work.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
hw/net/dp8393x.c | 47 +--
1 file changed, 29 insertions(+), 18 deleti
of
descriptors in this way.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
Changed since v1:
- Update CRDA register from LLFA register after EOL is cleared.
---
hw/net/dp8393x.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net
This function re-uses its 'size' argument as a scratch variable.
Instead, declare a local 'size' variable for that purpose so that the
function result doesn't get messed up.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Laurent Vivier
word boundary
(A0 and A1 are always zero).
This constraint has been implemented for 16-bit mode; implement it
for 32-bit mode too.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 8 ++--
1 file changed, 6 insertions(+), 2
. Fix this.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Laurent Vivier
---
hw/net/dp8393x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 0309365fda..947ceef37c 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -
It doesn't make sense to clear the command register bit unless the
command was actually issued.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Laurent Vivier
---
hw/net/dp8393x.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/h
On Wed, 29 Jan 2020, Philippe Mathieu-Daudé wrote:
> >
> > This would allow the host to change the value of the Silicon Revision
> > register.
> How the guest can modify it? We have:
>
> 589 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
> 590 unsi
On Tue, 28 Jan 2020, Philippe Mathieu-Daudé wrote:
> Hi Finn,
>
> On 1/19/20 11:59 PM, Finn Thain wrote:
> > The Least Significant bit of a descriptor address register is used as
> > an EOL flag. It has to be masked when the register value is to be used
> > as an
On Tue, 28 Jan 2020, Philippe Mathieu-Daud? wrote:
> On 1/19/20 11:59 PM, Finn Thain wrote:
> > The jazzsonic driver in Linux uses the Silicon Revision register value
> > to probe the chip. The driver fails unless the SR register contains 4.
> > Unfortunately, reading
On Mon, 20 Jan 2020, Finn Thain wrote:
> Hi All,
>
> There are bugs in the emulated dp8393x device that can stop packet
> reception in a Linux/m68k guest (q800 machine).
>
> With a Linux/mips guest (magnum machine), the driver fails to probe
> the dp8393x device.
>
turns false. This bug causes the SONIC to become
deaf (until reset).
Fix this with a new flag to indicate actual receive buffer exhaustion.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
Changed since v2:
- Don't use can_receive to suspend packet reception.
- Don't misuse th
These operations have to take place regardless of whether or not rx
descriptors have been used up (that is, EOL flag was observed).
The algorithm is the now the same for a packet that was withheld as
for a packet that was not.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
hw/net
The Least Significant bit of a descriptor address register is used as
an EOL flag. It has to be masked when the register value is to be used
as an actual address for copying memory around. But when the registers
are to be updated the EOL bit should not be masked.
Signed-off-by: Finn Thain
Tested
According to the datasheet, section 3.4.4, "in 32-bit mode ... the SONIC
always writes long words".
Therefore, use the same technique for the 'in_use' field that is used
everywhere else, and write the full long word.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
. Fix this.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Laurent Vivier
---
hw/net/dp8393x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 0309365fda..947ceef37c 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -
word (16-bit mode) or long word (32-bit mode)
if the last byte did not end on a word or long word boundary
respectively. The fill byte will be 0FFh.
Implement buffer padding so that buffer limits are correctly enforced.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
hw/net
It doesn't make sense to clear the command register bit unless the
command was actually issued.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Laurent Vivier
---
hw/net/dp8393x.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/h
This function re-uses its 'size' argument as a scratch variable.
Instead, declare a local 'size' variable for that purpose so that the
function result doesn't get messed up.
Signed-off-by: Finn Thain
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Laurent Vivier
patches.
Finn Thain (14):
dp8393x: Mask EOL bit from descriptor addresses
dp8393x: Always use 32-bit accesses
dp8393x: Clean up endianness hacks
dp8393x: Have dp8393x_receive() return the packet size
dp8393x: Update LLFA and CRDA registers from rx descriptor
dp8393x: Clear RRRA command
word boundary
(A0 and A1 are always zero).
This constraint has been implemented for 16-bit mode; implement it
for 32-bit mode too.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
hw/net/dp8393x.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/net
Linux 'jazzsonic' driver working, and avoids the need for
prior hacks to make the NetBSD 'sn' driver work.
Signed-off-by: Finn Thain
---
hw/net/dp8393x.c | 47 +--
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/hw/ne
of
descriptors in this way.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
Changed since v1:
- Update CRDA register from LLFA register after EOL is cleared.
---
hw/net/dp8393x.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net
RXpkt.in_use field.
The packet can now be processed by the host, so raise a PKTRX interrupt,
just like the normal case.
Signed-off-by: Finn Thain
Tested-by: Laurent Vivier
---
Changed since v2:
- Assert PKTRX interrupt when releasing withheld packet.
---
hw/net/dp8393x.c | 10 ++
1
quot;net/dp8393x: fix hardware reset")
Signed-off-by: Finn Thain
---
hw/net/dp8393x.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 1b73a8703b..71af0fad51 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -591,6 +591,10 @@ st
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