Register values are dumped as 'sz' chunks of two nibbles in the execlog
plugin, sz was 1 too big.
Signed-off-by: Frédéric Pétrot
---
contrib/plugins/execlog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execl
Le 11/01/2024 à 13:24, Alex Bennée a écrit :
Frédéric Pétrot writes:
Hello Alex,
just reporting below what might be a riscv only oddity (also applies to
patch 41 but easier to report here).
Le 03/01/2024 à 18:33, Alex Bennée a écrit :
With the new plugin register API we can now track
Hello Alex,
just reporting below what might be a riscv only oddity (also applies to
patch 41 but easier to report here).
Le 03/01/2024 à 18:33, Alex Bennée a écrit :
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb whi
Le 07/11/2023 à 11:31, Alex Bennée a écrit :
Frédéric Pétrot writes:
Hello Alex and Akihiko,
this patch introduces a regression for riscv.
When connecting to gdb, gdb issues the infamous "Architecture rejected
target-supplied description" warning.
I tracked it down to 13/29 when
t *obj)
{
CPUState *cpu = CPU(obj);
-CPUClass *cc = CPU_GET_CLASS(obj);
+gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
-cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
/* user-mode doe
Fix arch name in the define that prevents multiple inclusions.
Signed-off-by: Frédéric Pétrot
---
host/include/x86_64/host/atomic128-ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/host/include/x86_64/host/atomic128-ldst.h
b/host/include/x86_64/host/atomic128
Fixes: #1381
Signed-off-by: Emilio Cota
---
accel/tcg/plugin-gen.c| 44 ---
include/exec/plugin-gen.h | 4 ++--
include/qemu/plugin.h | 3 ---
tcg/tcg-op.c | 6 +++---
4 files changed, 28 insertions(+), 29 deletions(-)
Thanks Emilio for the fix, and Aaron for pointing it out to me.
Tested-by: Frédéric Pétrot
named-gpio-out[8]' not
found
This patch makes the nubering of the S irqs identical to what it was before.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Frédéric Pétrot
---
hw/intc/sifive_plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Le 14/11/2022 à 09:40, Philippe Mathieu-Daudé a écrit :
On 11/11/22 13:19, Frédéric Pétrot wrote:
Commit 40244040 changed the way the S irqs are numbered. This breaks when
40244040a7 in case?
Seems reasonnable, indeed, I'll even align with what git blame shows
(11 chars, so 402440
named-gpio-out[8]' not
found
This patch makes the nubering of the S irqs identical to what it was before.
Signed-off-by: Frédéric Pétrot
---
hw/intc/sifive_plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index
Hi Richard,
Le 11/07/2022 à 06:44, Richard Henderson a écrit :
On Sun, 10 July 2022, 16:36 Frédéric Pétrot,
<mailto:frederic.pet...@univ-grenoble-alpes.fr>> wrote:
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction that does not change processor state.
For rv128c right shifts, the 6-bit shamt is in addition sign extended to
7 bits.
Signed-off-by: Frédéric Pétrot
---
target/riscv/insn16.decode | 7
Le 09/07/2022 à 10:52, Weiwei Li a écrit :
在 2022/7/8 下午11:00, Frédéric Pétrot 写道:
For rv128c right shifts, the 6-bit shamt is sign extended to 7 bits.
Signed-off-by: Frédéric Pétrot
---
target/riscv/insn16.decode | 7 ---
disas/riscv.c | 27
For rv128c right shifts, the 6-bit shamt is sign extended to 7 bits.
Signed-off-by: Frédéric Pétrot
---
target/riscv/insn16.decode | 7 ---
disas/riscv.c | 27 +--
target/riscv/translate.c | 12 +++-
3 files changed, 36 insertions(+), 10
Add an MXL_RV128 case in two switches so that no error is triggered when
using the -cpu x-rv128 option.
Signed-off-by: Frédéric Pétrot
---
target/riscv/debug.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 2f2a51c732..fc6e13222f 100644
Le 09/04/2022 à 17:39, Richard Henderson a écrit :
On 4/9/22 02:46, Frédéric Pétrot wrote:
Now that we have misa xlen, use that in riscv gdbstub.c instead of the
TARGET_LONG_BITS define, and use riscv_cpu_mxl_bits to provide the number of
bits in a consistent way.
Signed-off-by: Frédéric
Since we now have xlen in misa, let's not use TARGET_LONG_BITS while
forging the isa string, and use instead riscv_cpu_mxl_bits.
Signed-off-by: Frédéric Pétrot
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/
Now that we have misa xlen, use that in riscv gdbstub.c instead of the
TARGET_LONG_BITS define, and use riscv_cpu_mxl_bits to provide the number of
bits in a consistent way.
Signed-off-by: Frédéric Pétrot
---
target/riscv/gdbstub.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions
Le 30/03/2022 à 04:08, Tsukasa OI a écrit :
On 2022/03/30 1:29, Frédéric Pétrot wrote:
Hello,
Le 28/03/2022 à 15:11, Tsukasa OI a écrit :
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
string. For instance, `S' and `U' (represents existence of superviso
Hello,
Le 28/03/2022 à 15:11, Tsukasa OI a écrit :
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
string. For instance, `S' and `U' (represents existence of supervisor
and user mode, respectively) in `misa' CSR must not be copied since
neither `S' nor `U' are valid single-let
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.
Signed-off-by: Frédéric Pétrot
---
target/riscv/cpu.c | 3 +--
target/riscv/gdbstub.c | 3 +++
2
Le 24/01/2022 à 09:47, LIU Zhiwei a écrit :
On 2022/1/24 下午3:49, Frédéric Pétrot wrote:
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, leading to the occurence of
"code should not be reached" in a few places.
This p
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, leading to the occurence of
"code should not be reached" in a few places.
This patch makes rv128 react as rv64 for gdb, as previously.
Signed-off-by: Frédéric Pétrot
---
ta
00 .. . 001 . 1011011 @sh6
--
+-------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://ti
On 07/01/2022 07:47, Alistair Francis wrote:
On Fri, Jan 7, 2022 at 4:23 PM Frédéric Pétrot
wrote:
On 06/01/2022 22:24, Alistair Francis wrote:
On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
wrote:
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64
On 06/01/2022 22:24, Alistair Francis wrote:
On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
wrote:
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit ins
, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 7 ++
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 195
version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/helper.h| 3 +++
target/riscv/csr.c
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
ta
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 10
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 4
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a
) we assume for now little-endian memory accesses.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode | 27 ++-
target/riscv/insn32.decode | 5 ++
target/riscv/translate.c| 41
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/ri
part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 9
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by
of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 20
1 file changed, 16 insertions
,
where they more logically belong.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 -
1 file changed, 17
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
i
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
include/exec/memop.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/exec/memop.h b
r rv128 for basic integer and M extension insns
Frédéric Pétrot (18):
exec/memop: Adding signedness to quad definitions
exec/memop: Adding signed quad and octo defines
qemu/int128: addition of div/rem 128-bit operations
target/riscv: additional macros to check instruction support
ta
On 06/01/2022 09:33, Alistair Francis wrote:
On Tue, Dec 14, 2021 at 2:39 AM Frédéric Pétrot
wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks again for the reviews and advices.
I think
, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/cpu.h | 7 ++
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 195 +---
3 files
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 4
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a
part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 3 +
target/riscv
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode | 10 ++
target/riscv/translate.c
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 9
version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 5 +
target/riscv/helper.h| 3 +++
target/riscv/csr.c | 17
) we assume for now little-endian memory accesses.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode | 27 ++-
target/riscv/insn32.decode | 5 ++
target/riscv/translate.c| 41
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
include/exec/memop.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/exec/memop.h b
Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
ta
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
i
,
where they more logically belong.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 -
1 file changed, 17
ger and M extension insns
Frédéric Pétrot (18):
exec/memop: Adding signedness to quad definitions
exec/memop: Adding signed quad and octo defines
qemu/int128: addition of div/rem 128-bit operations
target/riscv: additional macros to check instruction support
target/riscv: separation of bitwise log
of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 20
1 file changed, 16 insertions
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Hi Richard,
On 29/11/2021 13:13, Richard Henderson wrote:
On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks again for the reviews and suggestions.
v6
On 29/11/2021 11:07, Richard Henderson wrote:
On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
--- /dev/null
+++ b/util/int128.c
@@ -0,0 +1,145 @@
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "qemu/int128.h"
Missing file header and copyright boiler
On 29/11/2021 13:13, Richard Henderson wrote:
On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks again for the reviews and suggestions.
v6:
- support for
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode
part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 3 +
target/riscv
Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
ta
version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 4
target/riscv/helper.h| 3 +++
target/riscv/csr.c | 17
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/cpu.h | 7 ++
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 195 +---
3 files
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 20
1 file changed, 16 insertions
and M extension insns
Frédéric Pétrot (18):
exec/memop: Adding signedness to quad definitions
exec/memop: Adding signed quad and octo defines
qemu/int128: addition of div/rem 128-bit operations
target/riscv: additional macros to check instruction support
target/riscv: separation of bi
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode | 10 ++
target/riscv/translate.c
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 9
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 4
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a
) we assume for now little-endian memory accesses.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn16.decode | 27 ++-
target/riscv/insn32.decode | 5 ++
target/riscv/translate.c| 41 ++
target/riscv
,
where they more logically belong.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 -
1 file changed, 17 insertions(+), 17 deletions(-)
diff
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
i
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
include/exec/memop.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/exec/memop.h b
On 25/11/2021 12:47, Alistair Francis wrote:
On Wed, Nov 24, 2021 at 5:33 PM Philippe Mathieu-Daudé wrote:
Hi Frédéric,
On 11/24/21 07:55, Frédéric Pétrot wrote:
On 24/11/2021 07:12, Alistair Francis wrote:
On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
wrote:
This patch is kind of a
On 24/11/2021 07:12, Alistair Francis wrote:
On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
wrote:
This patch is kind of a mess because several files have to be slightly
modified to allow for a new target. In the current status, we have done
our best to have RV64 and RV128 under the same
On 23/11/2021 07:09, Alistair Francis wrote:
On Sat, Nov 13, 2021 at 1:07 AM Frédéric Pétrot
wrote:
+static bool rv128_needed(void *opaque)
+{
+RISCVCPU *cpu = opaque;
+CPURISCVState *env = &cpu->env;
+
+return env->misa_mxl_max == MXL_RV128;
+}
I think it would just be
On 15/11/2021 09:29, Richard Henderson wrote:
On 11/12/21 3:58 PM, Frédéric Pétrot wrote:
+ tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? desth : destl, addrl,
+ ctx->mem_idx, MO_TEUQ);
This isn't correct. MO_BSWAP is related to the host, not the guest.
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/translate.c | 21 +++--
1 file
part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 3 +
target/riscv
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 4
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv
,
where they more logically belong.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 -
meson | 2 +-
2 files
version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 4
target/riscv/helper.h| 3 +++
target/riscv/csr.c | 17
atomic accesses for aligned 128-bit addresses.
Once this patch applied, adding risc128-sofmmu to --target-list produces
a (no so useful yet) executable.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
configs/devices/riscv128-softmmu/default.mak | 17 +++
configs
-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn16.decode | 27 ++-
target/riscv/insn32.decode | 5 ++
target/riscv/translate.c| 41 ++
target/riscv/insn_trans/trans_rvi.c.inc | 102 ++--
4 files
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode | 10 ++
target/riscv/translate.c
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode
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