Re: [PATCH] ppc/xive: Fix uint32_t overflow

xive: Add support for the PC MMIOs") Signed-off-by: Cédric Le Goater --- Reviewed-by: Frederic Barrat hw/intc/pnv_xive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9b10e905195a..a36b3bf08c92 100644 --- a/hw/i

Re: [PATCH 4/4] ppc/xive: Add support for the PC MMIOs

by pnv_xive_vst_write or read to perform the operation in RAM. Remove the last use of pnv_xive_get_remote(). Signed-off-by: Cédric Le Goater - Nice cleanup Reviewed-by: Frederic Barrat Fred hw/intc/pnv_xive.c | 84 ++ 1 file changed, 48 insertions

Re: [PATCH 3/4] ppc/xive: Handle END triggers between chips with MMIOs

for the NVT accesses which we will address later. Signed-off-by: Cédric Le Goater --- Reviewed-by: Frederic Barrat Fred hw/intc/pnv_xive_regs.h | 1 + hw/intc/pnv_xive.c | 69 +++-- 2 files changed, 68 insertions(+), 2 deletions(-) diff --git

Re: [PATCH 2/4] ppc/xive: Introduce a new XiveRouter end_notify() handler

_W5_ESC_END_DATA, end.w5)); +xive_router_end_notify_handler(xrtr, (XiveEAS *) ); I didn't like the cast, but I can see why you're doing it this way. We should be fine as long as the notify handler is not testing the validity bit of the EAS structure. Reviewed-by: Frederic Barrat Fred } void xive_route

Re: [PATCH 1/4] ppc/xive: Use address_space routines to access the machine RAM

really to catch any error and remove any potential ambiguity about the address space? In any case, Reviewed-by: Frederic Barrat Fred +if (result != MEMTX_OK) { +xive_error(xive, "VST: read failed at @0x%" HWADDR_PRIx + " for VST %s %x/%x

Re: [PATCH for-8.2 2/3] pnv/lpc: Hook up xscom region for P9/P10

Hello Joel, So we're re-using the same xscom ops as on P8. A quick look at the definition of those 4 registers on P8 (0xb0020) and on P9/P10 (0x00090040) seem to show they are not the same though. Am i missing something? Fred On 08/08/2023 10:34, Joel Stanley wrote: From P9 on the LPC

[PATCH] pnv/xive: Print CPU target in all TIMA traces

Add the CPU target in the trace when reading/writing the TIMA space. It was already done for other TIMA ops (notify, accept, ...), only missing for those 2. Useful for debug and even more now that we experiment with SMT. Signed-off-by: Frederic Barrat --- hw/intc/trace-events | 4 ++-- hw/intc

[PATCH] pnv/xive2: Always pass a presenter object when accessing the TIMA

to figure out the presenter in that context, so this patch fixes it. Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 82fcd3ea22..bbb44a533c 100644 --- a/hw/intc/pnv_xive2.c

Re: [RFC PATCH 0/4] ppc: Improve multisocket support

On 04/07/2023 15:49, Cédric Le Goater wrote: Hello, Here are changes improving multisocket support of the XIVE models (POWER9 only). When a source has an END target on another chip, the XIVE IC will use an MMIO store to forward the notification to the remote chip. The long term plan is to

[PATCH] pnv/xive: Allow mmio operations of any size on the ESB CI pages

ESB pages for escalation interrupts defined for the ENDs. Signed-off-by: Frederic Barrat --- This should wrap-up the cleanup about mmio size for the xive BARs. The NVPG and NVC BAR accesses should also be relaxed but we don't really implement them, any load/store currently fails. Something to ad

Re: [PATCH v2 4/5] ppc/pnv: Add P10 core xscom model

On 04/07/2023 07:42, Joel Stanley wrote: Like the quad xscoms, add a core model for P10 to allow future differentiation from P9. Signed-off-by: Joel Stanley --- Reviewed-by: Frederic Barrat Fred hw/ppc/pnv_core.c | 44 ++-- 1 file changed

Re: [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom

On 04/07/2023 07:42, Joel Stanley wrote: Firmware now warns if booting in LPAR per core mode (PPC bit 62). So this warning doesn't trigger, report the core thread state is 0. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- Reviewed-by: Frederic Barrat Fred hw/ppc

Re: [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model

): xscom-core.1 00010014-00010093 (prio 0, i/o): xscom-core.0 Signed-off-by: Joel Stanley --- Reviewed-by: Frederic Barrat Fred v2: Fix unimp read message Wrap lines at 80 col Set size --- include/hw/ppc/pnv_xscom.h | 2 +- hw/ppc/pnv.c

Re: [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks

On 04/07/2023 07:42, Joel Stanley wrote: Make the existing pnv_quad_xscom_read/write be P9 specific, in preparation for a different P10 callback. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- Reviewed-by: Frederic Barrat Fred v2: Add scom region size to class

Re: [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific

On 04/07/2023 07:42, Joel Stanley wrote: Rename the functions to include P9 in the name in preparation for adding P10 versions. Correct the unimp read message while we're changing the function. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- Reviewed-by: Frederic Barrat

[PATCH v2 1/2] pnv/xive: Add property on xive sources to define PQ state on reset

The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Barrat --- hw/intc/xive.c| 8

[PATCH v2 2/2] pnv/psi: Initialize the PSIHB interrupts to match hardware

-by: Frederic Barrat --- hw/ppc/pnv_psi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 46da58dff8..daaa2f0575 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -863,6 +863,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp

[PATCH v2 0/2] Fix PSIHB interrupts init PQ state

it. Changelog: v2: rename property/struct member rebase to Daniel's ppc-next branch Frederic Barrat (2): pnv/xive: Add property on xive sources to define PQ state on reset pnv/psi: Initialize the PSIHB interrupts to match hardware hw/intc/xive.c| 8 ++-- hw/ppc/pnv_psi.c | 2

[PATCH v2] pnv/xive2: Fix TIMA offset for indirect access

the direct TIMA functions were accessing the privilege ring 0 page. With SMT4/8, it is no longer true. The fix is specific to P10, as indirect TIMA access on P9 was handled differently. Signed-off-by: Frederic Barrat --- Changelog: v2: rename function and variable rebase to Danel's ppc-next

[PATCH 0/2] Fix PSIHB interrupts init PQ state

it. Frederic Barrat (2): pnv/xive: Add property on xive sources to define PQ state on reset pnv/psi: Initialize the PSIHB interrupts to match hardware hw/intc/xive.c| 8 ++-- hw/ppc/pnv_psi.c | 2 ++ include/hw/ppc/xive.h | 1 + 3 files changed, 9 insertions(+), 2 deletions

[PATCH 1/2] pnv/xive: Add property on xive sources to define PQ state on reset

The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Barrat --- hw/intc/xive.c| 8

[PATCH 2/2] pnv/psi: Initialize the PSIHB interrupts to match hardware

On P9/P10, the PSIHB interrupts are initialized with a PQ state of 0b01, i.e. interrupts are disabled. However the real hardware initializes them to 0b00 for the PSIHB. This patch updates it, in case an hypervisor is in the mood of checking it. Signed-off-by: Frederic Barrat --- hw/ppc

[PATCH] pnv/xive2: Fix TIMA offset for indirect access

the direct TIMA functions were accessing the privilege ring 0 page. With SMT4/8, it is no longer true. The fix is specific to P10, as indirect TIMA access on P9 was handled differently. Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 19 +-- 1 file changed, 17

[PATCH] pnv/psi: Allow access to PSI registers through xscom

the existing mmio ops. Signed-off-by: Frederic Barrat --- hw/ppc/pnv_psi.c | 31 +-- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 8aa09ab26b..46da58dff8 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c

Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops

On 30/06/2023 05:55, Joel Stanley wrote: diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index b9a57463aec4..7fff2fd9e298 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, ... +

Re: [PATCH] hw/ppc: Fix clock update drift

! It must have been a nightmare to debug. Do you know where that ATB spr comes from? I can't relate it to the ISA. Reviewed-by: Frederic Barrat I also made a test case that can trigger this with kvm-unit-tests, but it's been taking me a while to get that upstreamed. Thanks, Nick hw/ppc/ppc.c | 33

Re: [PATCH] pnv/xive2: Allow indirect TIMA accesses of all sizes

On 26/06/2023 11:48, Philippe Mathieu-Daudé wrote: On 26/6/23 11:40, Frederic Barrat wrote: Booting linux on the powernv10 machine logs a few errors like: Invalid read at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason: invalid size (min:8 max:8) Invalid write at addr 0x38, size 1

[PATCH] pnv/xive2: Allow indirect TIMA accesses of all sizes

and the default "raw" handlers will pick up all other requests and complain about invalid sizes as appropriate. Tested-by: Nicholas Piggin Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/p

[PATCH v2 0/2] pnv/xive2: Fix TIMA special ops detection

Fix the TIMA special ops detection regression, as spotted by Coverity. Tested by running a pseries guest on top of a powernv9 and powernv10 host. Changelog: v2: define get_config for spapr Frederic Barrat (2): pnv/xive2: Add a get_config() method on the presenter class pnv/xive2: Check

[PATCH v2 2/2] pnv/xive2: Check TIMA special ops against a dedicated array for P10

ch. Fixes: Coverity CID 1512997, 1512998 Fixes: 6f2cbd133d4 ("pnv/xive2: Handle TIMA access through all ports") Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 32 hw/intc/xive.c | 52 + 2 files changed,

[PATCH v2 1/2] pnv/xive2: Add a get_config() method on the presenter class

Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive.c| 11 +++ hw/intc/pnv_xive2.c | 12 hw/intc/spapr_xive.c | 16 hw/intc/xive.c| 7 +++ include/hw/ppc/xive.h | 3 +++ 5 files changed, 49 insertions(+) diff --git a/hw/intc/pnv_xive.c

Re: [PATCH 1/2] pnv/xive2: Add a get_config() method on the presenter class

On 22/06/2023 09:01, Cédric Le Goater wrote: On 6/21/23 18:03, Frederic Barrat wrote: The presenters for xive on P9 and P10 are mostly similar but the behavior can be tuned through a few CQ registers. This patch adds a "get_config" method, which will allow to access that c

Re: [PATCH 0/2] pnv/xive2: Fix TIMA special ops detection

On 21/06/2023 19:23, Cédric Le Goater wrote: FYI, It is possible to force Gen1 on XIVE2 also. It you set the "capabilities" property on the command line :   -global driver=pnv-xive2,property=capabilities,value=0x1000120076f000FC Thanks, I hadn't noticed. And "config" too! Good to

[PATCH 1/2] pnv/xive2: Add a get_config() method on the presenter class

Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive.c| 11 +++ hw/intc/pnv_xive2.c | 12 hw/intc/xive.c| 7 +++ include/hw/ppc/xive.h | 3 +++ 4 files changed, 33 insertions(+) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 622f9d28b7..e536b3e

[PATCH 2/2] pnv/xive2: Check TIMA special ops against a dedicated array for P10

ch. Fixes: Coverity CID 1512997, 1512998 Fixes: 6f2cbd133d4 ("pnv/xive2: Handle TIMA access through all ports") Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 32 hw/intc/xive.c | 52 + 2 files changed,

[PATCH 0/2] pnv/xive2: Fix TIMA special ops detection

Fix the TIMA special ops detection regression, as spotted by Coverity. Tested by running a pseries guest on top of a powernv9 and powernv10 host. Frederic Barrat (2): pnv/xive2: Add a get_config() method on the presenter class pnv/xive2: Check TIMA special ops against a dedicated array

Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports

On 21/06/2023 09:18, Cédric Le Goater wrote: The XIVE2 TM ops are implemented with a shortcut (See the TODO in pnv_xive2_tm_*()). We could 1. extend xive_tctx_tm_write/read with a 'bool gen1_tima_os' parameter: xive_tctx_tm_write(xptr, tctx, offset, value, size, gen1_tima_os);    and

Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports

On 20/06/2023 13:20, Cédric Le Goater wrote: On 6/20/23 12:45, Peter Maydell wrote: On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza wrote: From: Frederic Barrat The Thread Interrupt Management Area (TIMA) can be accessed through 4 ports, targeted by the address. The base address

Re: [PATCH 3/9] MAINTAINERS: Add reviewer for XIVE

On 20/06/2023 07:59, Cédric Le Goater wrote: Fred discusses frequently with the IBM HW designers, he is fluent in XIVE logic, add him as a reviewer. Cc: Frédéric Barrat Signed-off-by: Cédric Le Goater --- Acked-by: Frederic Barrat Fred MAINTAINERS | 1 + 1 file changed, 1

Re: [PATCH 1/9] MAINTAINERS: Add reviewers for PowerNV baremetal emulation

-by: Frederic Barrat Fred MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 88b5a7ee0a79..e6f3dade2230 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1448,6 +1448,8 @@ F: tests/avocado/ppc_pseries.py PowerNV (Non-Virtualized) M: Cédric

[PATCH v2 3/5] pnv/xive2: Allow writes to the Physical Thread Enable registers

XIVE2 controller to the POWER10 chip") Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/intc/pnv_xive2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 9778c102ff..5fc4240216 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/p

[PATCH v2 4/5] pnv/xive2: Introduce macros to manipulate TIMA addresses

TIMA addresses are somewhat special and are split in several bit fields with different meanings. This patch describes it and introduce macros to more easily access the various fields. Signed-off-by: Frederic Barrat --- hw/intc/xive.c | 14 +++--- include/hw/ppc/xive_regs.h

[PATCH v2 5/5] pnv/xive2: Handle TIMA access through all ports

e) and P10 (xive2). Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 4 hw/intc/xive.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 5fc4240216..ec1edeb385 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/p

[PATCH v2 0/5] Various xive fixes

A set of small fixes for the interrupt controller (xive2) on P10. Change log: v2: split last patch to do a bit of cleanup first add Cedric's reviewed-by on the first 3 patches Frederic Barrat (5): pnv/xive2: Add definition for TCTXT Config register pnv/xive2: Add definition for the ESB

[PATCH v2 2/5] pnv/xive2: Add definition for the ESB cache configuration register

... XIVE[0] - VC: invalid read @240 XIVE[0] - VC: invalid write @240 Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/intc/pnv_xive2.c | 7 +++ hw/intc/pnv_xive2_regs.h | 4 2 files changed, 11 insertions(+) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c

[PATCH v2 1/5] pnv/xive2: Add definition for TCTXT Config register

] Initializing XIVE block ID 0... XIVE[0] - TCTXT: invalid read @140 XIVE[0] - TCTXT: invalid write @140 Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/intc/pnv_xive2.c | 8 +++- hw/intc/pnv_xive2_regs.h | 4 2 files changed, 11 insertions(+), 1 deletion(-) diff --git

[PATCH] pnv/xive2: Quiet down some error messages

ot), which is going to happen when dumping the xive state. So let's tune down those messages. They can be re-enabled easily with a macro if needed. Those errors were already hidden on xive/P9, for the same reason. Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 4 1 file changed, 4

Re: [PATCH 1/4] pnv/xive2: Add definition for TCTXT Config register

On 30/05/2023 18:31, Cédric Le Goater wrote: On 5/30/23 18:11, Frederic Barrat wrote: Add basic read/write support for the TCTXT Config register on P10. qemu doesn't do anything with it yet, but it avoids logging a guest error when skiboot configures the fused-core state: qemu-system-ppc64

Re: [PATCH 4/4] pnv/xive2: Handle TIMA access through all ports

On 30/05/2023 18:49, Cédric Le Goater wrote: On 5/30/23 18:40, Cédric Le Goater wrote: On 5/30/23 18:11, Frederic Barrat wrote: The Thread Interrupt Management Area (TIMA) can be accessed through 4 ports/snoop buses, targeted by the address. The base address of a TIMA is using port 0

Re: [PATCH 4/4] pnv/xive2: Handle TIMA access through all ports

On 30/05/2023 18:40, Cédric Le Goater wrote: On 5/30/23 18:11, Frederic Barrat wrote: The Thread Interrupt Management Area (TIMA) can be accessed through 4 ports/snoop buses, targeted by the address. The base address of a TIMA is using port 0 and the other ports are 0x80 apart. Using one

[PATCH 0/4] Various xive fixes

A set of small fixes for the interrupt controller (xive2) on P10. Frederic Barrat (4): pnv/xive2: Add definition for TCTXT Config register pnv/xive2: Add definition for the ESB cache configuration register pnv/xive2: Allow writes to the Physical Thread Enable registers pnv/xive2: Handle

[PATCH 4/4] pnv/xive2: Handle TIMA access through all ports

dress bits so that a TIMA operation can be triggered using any port. It is also true for indirect access (through the IC BAR) and it's actually nothing new, it was already the case on P9. Which helps here, as the TIMA handling code is common between P9 (xive) and P10 (xive2). Signed-off-by: Frederic Ba

[PATCH 2/4] pnv/xive2: Add definition for the ESB cache configuration register

... XIVE[0] - VC: invalid read @240 XIVE[0] - VC: invalid write @240 Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 7 +++ hw/intc/pnv_xive2_regs.h | 4 2 files changed, 11 insertions(+) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 889e409929..a75ff270ac

[PATCH 1/4] pnv/xive2: Add definition for TCTXT Config register

] Initializing XIVE block ID 0... XIVE[0] - TCTXT: invalid read @140 XIVE[0] - TCTXT: invalid write @140 Signed-off-by: Frederic Barrat --- hw/intc/pnv_xive2.c | 8 +++- hw/intc/pnv_xive2_regs.h | 4 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc

[PATCH 3/4] pnv/xive2: Allow writes to the Physical Thread Enable registers

Fix what was probably a silly mistake and allow to write the Physical Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET variant so it went unnoticed, but there's no reason to discard a write to the full register, it is Read-Write. Signed-off-by: Frederic Barrat --- hw/intc

Re: [PATCH] pnv_lpc: disable reentrancy detection for lpc-hc

Goater --- Reviewed-by: Frederic Barrat Thanks, Fred hw/ppc/pnv_lpc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 01f44c19ebba..605d3908617a 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -734,10 +734,13 @@ static void

Re: [PATCH v4] target/ppc: Add POWER9 DD2.2 model

On 15/05/2023 18:02, Nicholas Piggin wrote: POWER9 DD2.1 and earlier had significant limitations when running KVM, including lack of "mixed mode" MMU support (ability to run HPT and RPT mode on threads of the same core), and a translation prefetch issue which is worked around by disabling

Re: [PATCH v4] target/ppc: Add POWER9 DD2.2 model

disabling "AIL" mode for the guest. These processors are not widely available, and it's difficult to deal with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU and make it the default POWER9 CPU. Signed-off-by: Nicholas Piggin --- Reviewed-by: Frederic Barrat Which makes

Re: [PATCH] pnv_lpc: disable reentrancy detection for lpc-hc

On 11/05/2023 11:15, Alexander Bulekov wrote: On 230511 1104, Cédric Le Goater wrote: Hello Alexander On 5/11/23 10:53, Alexander Bulekov wrote: As lpc-hc is designed for re-entrant calls from xscom, mark it re-entrancy safe. Reported-by: Thomas Huth Signed-off-by: Alexander Bulekov ---

Re: [PATCH 1/4] pnv_phb4_pec: Keep track of instantiated PHBs

On 02/03/2023 23:21, Philippe Mathieu-Daudé wrote: Hi Frederic, On 2/3/23 17:37, Frederic Barrat wrote: Add an array on the PEC object to keep track of the PHBs which are instantiated. The array can be sparsely populated when using user-created PHBs. It will be useful for the next patch

[PATCH 1/4] pnv_phb4_pec: Keep track of instantiated PHBs

Add an array on the PEC object to keep track of the PHBs which are instantiated. The array can be sparsely populated when using user-created PHBs. It will be useful for the next patch to only export instantiated PHBs in the device tree. Signed-off-by: Frederic Barrat --- hw/pci-host

[PATCH 4/4] pnv_phb4_pec: Simplify/align code to parent user-created PHBs

or version. It's also easily extensible if we ever need to support a different parent object. Signed-off-by: Frederic Barrat --- hw/pci-host/pnv_phb.c | 11 ++- hw/pci-host/pnv_phb4_pec.c | 3 ++- hw/ppc/pnv.c | 29 - include/h

[PATCH 3/4] pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful file

() to hw/pci-host/pnv_phb4_pec.c, where it fits naturally. While at it, replace the PnvPHB4 parameter by the PnvPHB front-end, since it has all the information needed and simplify it a bit. No functional changes. Signed-off-by: Frederic Barrat --- hw/pci-host/pnv_phb4_pec.c | 40

[PATCH 2/4] pnv_phb4_pec: Only export existing PHBs to the device tree

exports PHBs which have been realized to the device tree. Fixes: d786be3fe746 ("ppc/pnv: enable user created pnv-phb for powernv9") Signed-off-by: Frederic Barrat --- hw/pci-host/pnv_phb4_pec.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_ph

[PATCH 0/4] user-created PHB cleanup

to only export the user-created PHBs in the device tree when 'nodefaults' is used. The last 2 are more cosmetic and moving code around where it makes more sense. Frederic Barrat (4): pnv_phb4_pec: Keep track of instantiated PHBs pnv_phb4_pec: Only export existing PHBs to the device tree

[PATCH 2/4] ppc/pnv/pci: Remove duplicate definition of PNV_PHB5_DEVICE_ID

PNV_PHB5_DEVICE_ID is defined in two different headers. The definition in hw/pci-host/pnv_phb4.h was left out in a previous rework. Remaining definition is in hw/pci-host/pnv_phb.h. Signed-off-by: Frederic Barrat --- include/hw/pci-host/pnv_phb4.h | 1 - 1 file changed, 1 deletion(-) diff

[PATCH 0/4] PCI-related cleanup for ppc/powernv

Pretty simple PCI-related cleanup for powernv Frederic Barrat (4): ppc/pnv/pci: Cleanup PnvPHBPecState structure ppc/pnv/pci: Remove duplicate definition of PNV_PHB5_DEVICE_ID ppc/pnv/pci: Update PHB5 version register ppc/pnv/pci: Fix PHB xscom registers memory region name hw/pci-host

[PATCH 4/4] ppc/pnv/pci: Fix PHB xscom registers memory region name

The name is for the region mapping the PHB xscom registers. It was apparently a bad cut-and-paste from the per-stack pci xscom area just above, so we had two regions with the same name. Signed-off-by: Frederic Barrat --- hw/pci-host/pnv_phb4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH 1/4] ppc/pnv/pci: Cleanup PnvPHBPecState structure

Remove unused structure member 'system_memory'. Signed-off-by: Frederic Barrat --- include/hw/pci-host/pnv_phb4.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 1f3237c9d5..17aef08f91 100644 --- a/include/hw/pci-host

[PATCH 3/4] ppc/pnv/pci: Update PHB5 version register

Update register value per its P10 DD2 definition. Signed-off-by: Frederic Barrat --- include/hw/pci-host/pnv_phb4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 761525686e..28d61b96c7 100644

Re: [PATCH v6 09/14] hw/ppc: set machine->fdt in pnv_reset()

On 05/09/2022 01:34, Daniel Henrique Barboza wrote: This will enable support for the 'dumpdtb' QMP/HMP command for all powernv machines. Cc: Cédric Le Goater Cc: Frederic Barrat Signed-off-by: Daniel Henrique Barboza --- LGTM Reviewed-by: Frederic Barrat Fred hw/ppc/pnv.c | 8

Re: [PATCH for-7.2 v2 2/2] ppc/pnv: fix QOM parenting of user creatable root ports

pnv_phb_attach_root_port() that was adding the root port as a child of the bus as well. After all that, remove pnv_phb_attach_root_port() and create the root port explictly in the 'default_enabled()' case of pnv_phb_realize(). Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat hw

Re: [PATCH for-7.2 v2 1/2] ppc/pnv: consolidate pnv_parent_*_fixup() helpers

. Next patch will make use of this function to handle a case where we need to change the QOM parent while keeping the same parent bus assigned beforehand. Signed-off-by: Daniel Henrique Barboza --- Thanks for the explanation. Reviewed-by: Frederic Barrat hw/pci-host/pnv_phb.c | 43

Re: [PATCH for-7.2 v4 06/11] ppc/pnv: enable user created pnv-phb for powernv8

relationship for user-created root port is not ideal, but it's addressed in the last patch of the series. Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 9 +++-- hw/ppc/pnv.c | 32 ++-- 2 files changed, 25 insertions(+), 16 deletions

Re: [PATCH for-7.2 v4 08/11] ppc/pnv: enable user created pnv-phb for powernv9

-created root port. Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 2 +- hw/pci-host/pnv_phb4_pec.c | 6 -- hw/ppc/pnv.c | 2 ++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 1f53ff77c5

Re: [PATCH for-7.2 v4 11/11] ppc/pnv: fix QOM parenting of user creatable root ports

On 11/08/2022 18:39, Daniel Henrique Barboza wrote: User creatable root ports are being parented by the 'peripheral' or the 'peripheral-anon' container. This happens because this is the regular QOM schema for sysbus devices that are added via the command line. Let's make this QOM hierarchy

Re: [PATCH for-7.2 v4 10/11] ppc/pnv: user creatable pnv-phb for powernv10

--- Reviewed-by: Frederic Barrat Fred hw/ppc/pnv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e6c14fe231..9bf35ca9d6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2226,6 +2226,8 @@ static void pnv_machine_power10_class_init(ObjectClass *oc

Re: [PATCH for-7.2 v4 09/11] ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs

-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/ppc/pnv.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ec0558ed1c..e6c14fe231 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -284,17 +284,30

Re: [PATCH for-7.2 v4 07/11] ppc/pnv: add PHB4 helpers for user created pnv-phb

ue Barboza --- Reviewed-by: Frederic Barrat Fred hw/ppc/pnv.c | 35 --- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e82d6522f0..0644f45a1d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -281,6 +281,34

Re: [PATCH for-7.2 v4 05/11] ppc/pnv: turn chip8->phbs[] into a PnvPHB* array

happen with the user created case: the object is created, parented by the chip because pnv_xscom_dt() relies on it, and then assigned to the array. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/ppc/pnv.c | 27 ++- include/hw/ppc

Re: [PATCH for-7.2 v4 04/11] ppc/pnv: add helpers for pnv-phb user devices

ingle spot, leaving the realize functions of the phb3/phb4 backends untouched. Another helper called pnv_chip_add_phb() was added to handle the particularities of each chip version when adding a new PHB. Signed-off-by: Daniel Henrique Barboza --- Just a minor typo in a comment below. Reviewed-by

Re: [PATCH for-7.2 v4 01/11] ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties

reated and default root ports, without doing anything too shady with QOM. Reviewed-by: Cédric Le Goater Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb3.c | 50 ++ include/hw/pci-host/pnv_phb3.

Re: [PATCH for-7.2 v4 03/11] ppc/pnv: set root port chassis and slot using Bus properties

these changes with the existing default devices. Reviewed-by: Cédric Le Goater Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 25 - 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/pci-host

Re: [PATCH for-7.2 v4 02/11] ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties

the root port limit for phb4/5 later on without having to deal with phb3 code. Reviewed-by: Cédric Le Goater Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb4.c | 51 ++ include/hw/pci-host/pnv_phb4.h

Re: [PATCH for-7.2 00/10] enable pnv-phb user created devices

Hi Daniel, Other than my comment on patch 6 regarding the qom parenting of the root port, that series looks pretty good to me! Fred On 03/08/2022 15:44, Daniel Henrique Barboza wrote: Hi, This is a rebase on top of ppc-7.2 of the previous patches sent here:

Re: [PATCH for-7.2 v2 09/20] hw/ppc: set machine->fdt in pnv_reset()

On 05/08/2022 11:39, Daniel Henrique Barboza wrote: This will enable support for 'dumpdtb' and 'info fdt' HMP commands for all powernv machines. Cc: Cédric Le Goater Cc: Frederic Barrat Signed-off-by: Daniel Henrique Barboza --- hw/ppc/pnv.c | 6 +- 1 file changed, 5 insertions

Re: [PATCH for-7.2 06/10] ppc/pnv: enable user created pnv-phb for powernv8

diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 077f391d59..953c384bf6 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -17,6 +17,7 @@ #include "hw/ppc/pnv.h" #include "hw/qdev-properties.h" #include "qom/object.h" +#include "sysemu/sysemu.h" /*

Re: [PATCH for-7.2 04/10] ppc/pnv: add helpers for pnv-phb user devices

On 03/08/2022 15:44, Daniel Henrique Barboza wrote: pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices". They are needed to amend the QOM and bus hierarchies of user created

Re: [PATCH v3 05/12] ppc/pnv: turn PnvPHB4 into a PnvPHB backend

we could remove the second if statement for readability. The reason I mention it is that we don't take that much care in the pnv_chip_power8_pic_print_info() function just above, so it looks a bit odd. In any case: Reviewed-by: Frederic Barrat Fred @@ -2122,8 +2129,14 @@ st

Re: [PATCH v3 10/12] ppc/pnv: remove pecc->rp_model

On 24/06/2022 10:49, Daniel Henrique Barboza wrote: The attribute is unused. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb4_pec.c | 2 -- include/hw/pci-host/pnv_phb4.h | 1 - 2 files changed, 3 deletions(-) diff --git

Re: [PATCH v3 09/12] ppc/pnv: remove root port name from pnv_phb_attach_root_port()

On 24/06/2022 10:49, Daniel Henrique Barboza wrote: We support only a single root port, PNV_PHB_ROOT_PORT. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 7 +-- hw/ppc/pnv.c | 9 + include/hw/ppc/pnv.h

Re: [PATCH v3 06/12] ppc/pnv: add pnv-phb-root-port device

-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 115 +++--- hw/pci-host/pnv_phb.h | 16 ++ 2 files changed, 123 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c

Re: [PATCH v3 12/12] ppc/pnv: move attach_root_port helper to pnv-phb.c

On 24/06/2022 10:49, Daniel Henrique Barboza wrote: The helper is only used in this file. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 24 hw/ppc/pnv.c | 25

Re: [PATCH v3 08/12] ppc/pnv: remove pnv-phb4-root-port

-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 4 +- hw/pci-host/pnv_phb4.c | 85 -- hw/pci-host/pnv_phb4_pec.c | 4 +- hw/ppc/pnv.c | 2 + include/hw/pci-host/pnv_phb4.h | 9 5 files changed, 6 insertions(+), 98

Re: [PATCH v3 11/12] ppc/pnv: remove PnvPHB4.version

On 24/06/2022 10:49, Daniel Henrique Barboza wrote: It's unused. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred include/hw/pci-host/pnv_phb4.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host

Re: [PATCH v3 02/12] ppc/pnv: add PnvPHB base/proxy device

oza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/meson.build | 3 +- hw/pci-host/pnv_phb.c | 124 hw/pci-host/pnv_phb.h | 39 + 3 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 hw/pci-host/pnv_phb.c cre

Re: [PATCH v3 07/12] ppc/pnv: remove pnv-phb3-root-port

-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 2 +- hw/pci-host/pnv_phb3.c | 42 -- hw/ppc/pnv.c | 1 + include/hw/pci-host/pnv_phb3.h | 6 - 4 files changed, 2 insertions(+), 49 deletions(-) diff --git a/hw/pci

Re: [PATCH v3 04/12] ppc/pnv: add PHB4 bus init helper

-by: Frederic Barrat Fred hw/pci-host/pnv_phb.c | 2 ++ hw/pci-host/pnv_phb4.c | 39 -- include/hw/pci-host/pnv_phb4.h | 1 + 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c

Re: [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper

device and put into a new parent PnvPHB device. The new pnv_phb3_bus_init() helper will be used by the parent to init the bus when using the PHB3 backend. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Frederic Barrat Fred hw/pci-host/pnv_phb3.c | 39

Re: [PATCH v3 03/12] ppc/pnv: turn PnvPHB3 into a PnvPHB backend

ult settings. The real gain will come with user created PnvPHB devices, coming up next. Signed-off-by: Daniel Henrique Barboza --- A very minor indentation issue below, but other than that: Reviewed-by: Frederic Barrat hw/pci-host/pnv_phb3.c | 27 +-- hw/ppc/pn

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