Re: [PATCH v10 12/12] target/riscv: Update the privilege field for sscofpmf CSRs

Am Dienstag, 21. Juni 2022, 01:16:02 CEST schrieb Atish Patra: > The sscofpmf extension was ratified as a part of priv spec v1.12. > Mark the csr_ops accordingly. > > Reviewed-by: Alistair Francis > Signed-off-by: Atish Patra Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner > --- >

Re: [PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree

Hi Atish, Am Dienstag, 21. Juni 2022, 01:16:01 CEST schrieb Atish Patra: > Qemu virt machine can support few cache events and cycle/instret counters. > It also supports counter overflow for these events. > > Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine > capabilities.

Re: [PATCH v10 09/12] target/riscv: Simplify counter predicate function

Am Dienstag, 21. Juni 2022, 01:15:59 CEST schrieb Atish Patra: > All the hpmcounters and the fixed counters (CY, IR, TM) can be represented > as a unified counter. Thus, the predicate function doesn't need handle each > case separately. > > Simplify the predicate function so that we just handle

Re: [PATCH v10 10/12] target/riscv: Add few cache related PMU events

Am Dienstag, 21. Juni 2022, 01:16:00 CEST schrieb Atish Patra: > From: Atish Patra > > Qemu can monitor the following cache related PMU events through > tlb_fill functions. > > 1. DTLB load/store miss > 3. ITLB prefetch miss > > Increment the PMU counter in tlb_fill function. > > Reviewed-by:

Re: [PATCH v10 08/12] target/riscv: Add sscofpmf extension support

Am Dienstag, 21. Juni 2022, 01:15:58 CEST schrieb Atish Patra: > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, > and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) > extension allows the perf to handle overflow interrupts and filtering > support. This patch

Re: [RFC PATCH v3] RISC-V: Add Zawrs ISA extension support

Am Donnerstag, 23. Juni 2022, 17:29:07 CEST schrieb Christoph Muellner: > This patch adds support for the Zawrs ISA extension. > Given the current (incomplete) implementation of reservation sets > there seems to be no way to provide a full emulation of the WRS > instruction (wake on reservation

Re: [RFC PATCH v2] RISC-V: Add Zawrs ISA extension support

Am Donnerstag, 2. Juni 2022, 15:40:17 CEST schrieb Christoph Muellner: > From: Christoph Muellner > > This patch adds support for the Zawrs ISA extension. > Given the current (incomplete) implementation of reservation sets > there seems to be no way to provide a full emulation of the WRS >

Re: [PATCH 1/1] Add Zihintpause support

Am Dienstag, 10. Mai 2022, 08:42:31 CEST schrieb Dao Lu: > Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld > by default. > > Signed-off-by: Dao Lu This patch with your fixup applied to it and of course a matching kernel: Tested-by: Heiko Stuebner > --- >

Re: [PATCH v2] target/riscv: Add isa extenstion strings to the device tree

Am Mittwoch, 16. Februar 2022, 01:09:04 CET schrieb Atish Patra: > The Linux kernel parses the ISA extensions from "riscv,isa" DT > property. It used to parse only the single letter base extensions > until now. A generic ISA extension parsing framework was proposed[1] > recently that can parse

Re: [PATCH] target/riscv: Add isa extenstion strings to the device tree

Am Dienstag, 15. Februar 2022, 20:39:10 CET schrieb Atish Patra: > On Tue, Feb 15, 2022 at 8:20 AM Heiko Stübner wrote: > > > > Am Dienstag, 15. Februar 2022, 10:05:30 CET schrieb Atish Patra: > > > Append the available ISA extensions to the "riscv,isa"

Re: [PATCH] target/riscv: Add isa extenstion strings to the device tree

Am Dienstag, 15. Februar 2022, 10:05:30 CET schrieb Atish Patra: > Append the available ISA extensions to the "riscv,isa" string if it > is enabled so that kernel can process it. > > Signed-off-by: Atish Patra > --- > target/riscv/cpu.c | 23 ++- > 1 file changed, 22

Re: [PATCH] target/riscv: Add isa extenstion strings to the device tree

Hi Atish, Am Dienstag, 15. Februar 2022, 10:05:30 CET schrieb Atish Patra: > Append the available ISA extensions to the "riscv,isa" string if it > is enabled so that kernel can process it. For people glancing at these patches, a bit more insight into how the isa string comes together might be

Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support

Hi Atish, Am Donnerstag, 20. Januar 2022, 21:07:34 CET schrieb Atish Patra: > The RISC-V privileged specification v1.12 defines few execution > environment configuration CSRs that can be used enable/disable > extensions per privilege levels. > > Add the basic support for these CSRs. > >