[PATCH for-5.1 V3 2/7] hw/mips: Implement the kvm_type() hook in MachineClass

a VZ platform. Thus, null-machine also need the kvm_type() hook. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- hw/core/Makefile.objs | 2 +- hw/core/null-machine.c | 4 hw/mips/Makefile.objs | 2 +- hw/mips/common.c | 31 +++ include/hw/mips

[PATCH for-5.1 V3 1/7] configure: Add KVM target support for MIPS64

Preparing for Loongson-3 virtualization, add KVM target support for MIPS64 in configure script. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index 23b5e93..7581e65 100755 --- a

[PATCH for-5.1 V3 0/7] mips: Add Loongson-3 machine support (with KVM)

type for TCG/KVM automatically. V1 -> V2: 1, Add a cover letter; 2, Improve CPU definitions; 3, Remove LS7A-related things (Use GPEX instead); 4, Add a description of how to run QEMU/Loongson-3. V2 -> V3: 1, Fix all possible checkpatch.pl errors and warnings. Huacai Chen(7): configure: Ad

[PATCH V3 13/14] KVM: MIPS: Add more MMIO load/store instructions emulation

This patch add more MMIO load/store instructions emulation, which can be observed in QXL and some other device drivers: 1, LWL, LWR, LDW, LDR, SWL, SWR, SDL and SDR for all MIPS; 2, GSLBX, GSLHX, GSLWX, GSLDX, GSSBX, GSSHX, GSSWX and GSSDX for Loongson-3. Signed-off-by: Huacai Chen Co

[PATCH V3 14/14] KVM: MIPS: Enable KVM support for Loongson-3

VCPUs. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/Kconfig| 1 + arch/mips/kernel/cpu-probe.c | 1 + arch/mips/kvm/vz.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9f15539..9c4bdac

[PATCH V3 12/14] KVM: MIPS: Add CONFIG6 and DIAG registers emulation

Loongson-3 has CONFIG6 and DIAG registers which need to be emulate. CONFIG6 is mostly used to enable/disable FTLB and SFB, while DIAG is mostly used to flush BTB, ITLB, DTLB, VTLB and FTLB. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 7

[PATCH V3 11/14] KVM: MIPS: Add CPUCFG emulation for Loongson-3

duced feature list (which means the virtual CPU doesn't have any other advanced features, including CSR) in KVM. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 3 ++ arch/mips/include/uapi/asm/inst.h | 11 ++ arch/mips/kvm/mips.c

[PATCH V3 09/14] KVM: MIPS: Add more types of virtual interrupts

mapping tables: kvm_loongson3_priority_to_irq[] for Loongson-3, and kvm_default_priority_to_irq[] for others. The virtual interrupt infrastructure is updated to deliver all types of interrupts from IP2, IP3, IP4, IP6 and IP7. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips

[PATCH V3 10/14] KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support

This patch add Loongson-3 Virtual IPI interrupt support in the kernel, because emulate it in QEMU is too expensive for performance. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 32 ++ arch/mips/kvm/Makefile | 3 + arch/mips/kvm

[PATCH V3 08/14] KVM: MIPS: Let indexed cacheops cause guest exit on Loongson-3

Loongson-3's indexed cache operations need a node-id in the address, but in KVM guest the node-id may be incorrect. So, let indexed cache operations cause guest exit on Loongson-3. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/vz.c | 8 ++-- 1 file chang

[PATCH V3 07/14] KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3

s all guest mappings be cacheable mappings. Thus, we use root tlb to control guest's CCA for Loongson-3. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/vz.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c ind

[PATCH V3 06/14] KVM: MIPS: Introduce and use cpu_guest_has_ldpte

Loongson-3 has lddir/ldpte instructions and their related CP0 registers are the same as HTW. So we introduce a cpu_guest_has_ldpte flag and use it to indicate whether we need to save/restore HTW related CP0 registers (PWBase, PWSize, PWField and PWCtl). Signed-off-by: Huacai Chen Co-developed-by

[PATCH V3 05/14] KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd

Loongson-3 can use lddir/ldpte instuctions to accelerate page table walking, so use them to lookup gpa_mm.pgd. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/entry.c | 19 ++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/mips/kvm

[PATCH V3 04/14] KVM: MIPS: Add EVENTFD support which is needed by VHOST

Add EVENTFD support for KVM/MIPS, which is needed by VHOST. Tested on Loongson-3 platform. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/Kconfig | 1 + arch/mips/kvm/Makefile| 2 +- arch/mips/kvm/trap_emul.c | 3 +++ arch/mips/kvm/vz.c| 3 +++ 4

qemu-devel@nongnu.org

rder to support variable ASID_MASK, KVM_ENTRYHI_ASID should also be changed to cpu_asid_mask(&boot_cpu_data). Cc: sta...@vger.kernel.org Signed-off-by: Xing Li [Huacai: Change current_cpu_data to boot_cpu_data for optimization] Signed-off-by: Huacai Chen --- arch/mips/include/asm/kvm_host.

[PATCH V3 03/14] KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16

Loongson-3 based machines can have as many as 16 CPUs, and so does memory slots, so increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[PATCH V3 02/14] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits

definition. Cc: sta...@vger.kernel.org Signed-off-by: Xing Li [Huacai: Improve commit messages] Signed-off-by: Huacai Chen --- arch/mips/include/asm/kvm_host.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index a01cee9

[PATCH V3 00/14] KVM: MIPS: Add Loongson-3 support (Host Side)

de be guarded by CONFIG_CPU_LOONGSON64. V2 -> V3: 1, Emulate a reduced feature list of CPUCFG. 2, Fix all possible checkpatch.pl errors and warnings. Xing Li(2): KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(&boot_cpu_data) KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vm

[PATCH for-5.1 V2 6/7] hw/mips: Add Loongson-3 machine support (with KVM)

be omitted here and QEMU will use the correct type for TCG/KVM automatically. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- default-configs/mips64el-softmmu.mak | 1 + hw/mips/Kconfig | 10 + hw/mips/Makefile.objs| 1 + hw/mips/mips_l

[PATCH for-5.1 V2 5/7] target/mips: Add more CP0 register for save/restore

Add more CP0 register for save/restore, including: EBase, XContext, PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- target/mips/kvm.c | 212 ++ target/mips

[PATCH for-5.1 V2 7/7] MAINTAINERS: Add myself as Loongson-3 maintainer

Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aa9a057..66c5a41 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1080,6 +1080,11 @@ F: hw/isa/vt82c686.c F: hw/pci-host/bonito.c F

[PATCH for-5.1 V2 2/7] hw/mips: Implement the kvm_type() hook in MachineClass

a VZ platform. Thus, null-machine also need the kvm_type() hook. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- hw/core/Makefile.objs | 2 +- hw/core/null-machine.c | 4 hw/mips/Makefile.objs | 2 +- hw/mips/common.c | 29 + include/hw/mips

[PATCH for-5.1 V2 4/7] target/mips: Add Loongson-3 CPU definition

add their bit-fields as well. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- target/mips/cpu.h| 28 ++ target/mips/internal.h | 2 + target/mips/mips-defs.h | 7 +++- target/mips/translate.c | 2 + target/mips/trans

[PATCH for-5.1 V2 1/7] configure: Add KVM target support for MIPS64

Preparing for Loongson-3 virtualization, add KVM target support for MIPS64 in configure script. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index 23b5e93..7581e65 100755 --- a

[PATCH for-5.1 V2 3/7] hw/mips: Add CPU IRQ3 delivery for KVM

Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add IP3 delivery as well, because Loongson-3 based machine use both IRQ2 (CPU's IP2) and IRQ3 (CPU's IP3). Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- hw/mips/mips_int.c | 6 ++ 1 file changed, 2

[PATCH for-5.1 V2 0/7] mips: Add Loongson-3 machine support (with KVM)

ips64el -M loongson3,accel=tcg -cpu Loongson-3A1000 -kernel -append ... Use QEMU with KVM (available at present): qemu-system-mips64el -M loongson3,accel=kvm -cpu Loongson-3A4000 -kernel -append ... The "-cpu" parameter can be omitted here and QEMU will use the correct ty

Re: [PATCH for-5.1 3/7] hw/mips: Add CPU IRQ3 delivery for KVM

Hi, Philippe, On Wed, Apr 29, 2020 at 5:18 PM Philippe Mathieu-Daudé wrote: > > On 4/29/20 3:52 AM, Huacai Chen wrote: > > Hi, Philippe and Aleksandar, > > > > I'm not refusing to change my patch, but I have two questions: > > 1, Why we should identify Loong

Re: [PATCH for-5.1 4/7] target/mips: Add Loongson-3 CPU definition

Hi, Philippe, On Wed, Apr 29, 2020 at 5:30 PM Philippe Mathieu-Daudé wrote: > > On 4/29/20 11:25 AM, Huacai Chen wrote: > > Hi, Philippe, > > > > I think that this CPU definition is for Guest, not for Host (Maybe I'm > > wrong?). > > OK, it was not ob

Re: [PATCH for-5.1 4/7] target/mips: Add Loongson-3 CPU definition

Hi, Philippe, I think that this CPU definition is for Guest, not for Host (Maybe I'm wrong?). On Wed, Apr 29, 2020 at 4:58 PM Philippe Mathieu-Daudé wrote: > > On 4/29/20 10:27 AM, Huacai Chen wrote: > > Hi, Philippe, > > > > The major differences of R3 and R4 are

Re: [PATCH for-5.1 4/7] target/mips: Add Loongson-3 CPU definition

4:09 PM Philippe Mathieu-Daudé wrote: > > On 4/29/20 5:51 AM, Huacai Chen wrote: > > Hi, Aleksandar, > > > > I've tried translate.google.com, and documents are available here: > > Loongson-3A R1 (Loongson-3A1000) > > User Manual Part 1: > > h

Re: [PATCH for-5.1 4/7] target/mips: Add Loongson-3 CPU definition

pr 28, 2020 at 2:34 PM Philippe Mathieu-Daudé > > wrote: > > > > > > Hi Huacai, > > > > > > On 4/27/20 11:33 AM, Huacai Chen wrote: > > > > Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B > > > > R1/R2. Loongson-3A

Re: [PATCH for-5.1 3/7] hw/mips: Add CPU IRQ3 delivery for KVM

t; wrote: > > > > > > On 4/27/20 11:33 AM, Huacai Chen wrote: > > > > Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add > > > > IP2 delivery as well, because Loongson-3 based machine use both IRQ2 > > > > (CPU's IP2) an

Re: [PATCH for-5.1 6/7] hw/mips: Add Loongson-3 machine support (with KVM)

than > one example is better than only one. > > Specifically, can you explicitly say what is your KVM setup, so that > anyone could repro it? > > Good health to people from China! > Thank you very much, I will improve that in V2. > Yours, > Aleksandar > >

Re: [PATCH for-5.1 5/7] target/mips: Add more CP0 register for save/restore

Hi, Aleksandar, On Wed, Apr 29, 2020 at 3:10 AM Aleksandar Markovic wrote: > > пон, 27. апр 2020. у 11:36 Huacai Chen је написао/ла: > > > > Add more CP0 register for save/restore, including: EBase, XContext, > > PageGrain, PWBase, PWSize, PWField, PWCtl, Conf

[PATCH for-5.1 7/7] MAINTAINERS: Add myself as Loongson-3 maintainer

Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aa9a057..efe840b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1080,6 +1080,12 @@ F: hw/isa/vt82c686.c F: hw/pci-host/bonito.c F

[PATCH for-5.1 6/7] hw/mips: Add Loongson-3 machine support (with KVM)

Add Loongson-3 based machine support, it use i8259 as the interrupt controler and use GPEX as the pci controller. Currently it can only work with KVM, but we will add TCG support in future. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- default-configs/mips64el-softmmu.mak | 1

[PATCH for-5.1 5/7] target/mips: Add more CP0 register for save/restore

Add more CP0 register for save/restore, including: EBase, XContext, PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- target/mips/kvm.c | 212 ++ target/mips

[PATCH for-5.1 4/7] target/mips: Add Loongson-3 CPU definition

G7, so add their bit-fields as well. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- target/mips/cpu.h| 28 ++ target/mips/internal.h | 2 ++ target/mips/mips-defs.h | 7 -- target/mips/translate.c | 2 ++ t

[PATCH for-5.1 3/7] hw/mips: Add CPU IRQ3 delivery for KVM

Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add IP2 delivery as well, because Loongson-3 based machine use both IRQ2 (CPU's IP2) and IRQ3 (CPU's IP3). Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- hw/mips/mips_int.c | 6 ++ 1 file changed, 2

[PATCH for-5.1 2/7] hw/mips: Implement the kvm_type() hook in MachineClass

a VZ platform. Thus, null-machine also need the kvm_type() hook. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- hw/core/Makefile.objs | 2 +- hw/core/null-machine.c | 4 hw/mips/Makefile.objs | 2 +- hw/mips/common.c | 29 + include/hw/mips

[PATCH for-5.1 1/7] configure: Add KVM target support for MIPS64

Preparing for Loongson-3 virtualization, add KVM target support for MIPS64 in configure script. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index 23b5e93..7581e65 100755 --- a

Re: [PATCH 13/15] KVM: MIPS: Add CONFIG6 and DIAG registers emulation

Hi, Jiaxun, Thank you for your suggestion, in this patch and the 8th patch I will use CONFIG_CPU_LOONGSON64. Huacai On Mon, Apr 13, 2020 at 7:19 PM Jiaxun Yang wrote: > > On Mon, 13 Apr 2020 15:30:22 +0800 > Huacai Chen wrote: > > > Loongson-3 has CONFIG6 and DIAG register

Re: [PATCH 0/15] KVM: MIPS: Add Loongson-3 support (Host Side)

Hi, all, On Tue, Apr 14, 2020 at 12:45 PM Jiaxun Yang wrote: > > On Tue, 14 Apr 2020 09:40:26 +0800 > maobibo wrote: > > > On 04/13/2020 04:18 PM, Jiaxun Yang wrote: > > > On Mon, 13 Apr 2020 15:30:09 +0800 > > > Huacai Chen wrote: > > > > >

Re: [PATCH 0/15] KVM: MIPS: Add Loongson-3 support (Host Side)

Hi, Jiaxun, On Mon, Apr 13, 2020 at 4:19 PM Jiaxun Yang wrote: > > On Mon, 13 Apr 2020 15:30:09 +0800 > Huacai Chen wrote: > > > We are preparing to add KVM support for Loongson-3. VZ extension is > > fully supported in Loongson-3A R4+, and we will not care about old >

[PATCH 15/15] KVM: MIPS: Enable KVM support for Loongson-3

VCPUs. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/Kconfig| 1 + arch/mips/kernel/cpu-probe.c | 1 + arch/mips/kvm/vz.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a1f973c..e9a1389

[PATCH 14/15] KVM: MIPS: Add more MMIO load/store instructions emulation

This patch add more MMIO load/store instructions emulation, which can be observed in QXL and some other device drivers: 1, LWL, LWR, LDW, LDR, SWL, SWR, SDL and SDR for all MIPS; 2, GSLBX, GSLHX, GSLWX, GSLDX, GSSBX, GSSHX, GSSWX and GSSDX for Loongson-3. Signed-off-by: Huacai Chen Co

[PATCH 13/15] KVM: MIPS: Add CONFIG6 and DIAG registers emulation

Loongson-3 has CONFIG6 and DIAG registers which need to be emulate. CONFIG6 is mostly used to enable/disable FTLB and SFB, while DIAG is mostly used to flush BTB, ITLB, DTLB, VTLB and FTLB. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 5

[PATCH 11/15] KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support

This patch add Loongson-3 Virtual IPI interrupt support in the kernel, because emulate it in QEMU is too expensive for performance. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 32 ++ arch/mips/kvm/Makefile | 3 + arch/mips/kvm

[PATCH 12/15] KVM: MIPS: Add CPUCFG emulation for Loongson-3

means the virtual CPU doesn't have any advanced features, including CSR) in KVM. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 3 +++ arch/mips/include/uapi/asm/inst.h | 11 + arch/mips/kvm/mips.c | 3 +++ arch/mip

[PATCH 10/15] KVM: MIPS: Add more types of virtual interrupts

mapping tables: kvm_loongson3_priority_to_irq[] for Loongson-3, and kvm_default_priority_to_irq[] for others. The virtual interrupt infrastructure is updated to deliver all types of interrupts from IP2, IP3, IP4, IP6 and IP7. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips

[PATCH 09/15] KVM: MIPS: Let indexed cacheops cause guest exit on Loongson-3

Loongson-3's indexed cache operations need a node-id in the address, but in KVM guest the node-id may be incorrect. So, let indexed cache operations cause guest exit on Loongson-3. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/vz.c | 8 ++-- 1 file chang

[PATCH 08/15] KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3

s all guest mappings be cacheable mappings. Thus, we use root tlb to control guest's CCA for Loongson-3. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/vz.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c ind

[PATCH 03/15] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits

definition. Cc: sta...@vger.kernel.org Signed-off-by: Xing Li [Huacai: Improve commit messages] Signed-off-by: Huacai Chen --- arch/mips/include/asm/kvm_host.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 5794584

[PATCH 06/15] KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd

Loongson-3 can use lddir/ldpte instuctions to accelerate page table walking, so use them to lookup gpa_mm.pgd. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/entry.c | 19 ++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/mips/kvm

[PATCH 07/15] KVM: MIPS: Introduce and use cpu_guest_has_ldpte

Loongson-3 has lddir/ldpte instructions and their related CP0 registers are the same as HTW. So we introduce a cpu_guest_has_ldpte flag and use it to indicate whether we need to save/restore HTW related CP0 registers (PWBase, PWSize, PWField and PWCtl). Signed-off-by: Huacai Chen Co-developed-by

[PATCH 05/15] KVM: MIPS: Add EVENTFD support which is needed by VHOST

Add EVENTFD support for KVM/MIPS, which is needed by VHOST. Tested on Loongson-3 platform. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/kvm/Kconfig | 1 + arch/mips/kvm/Makefile| 2 +- arch/mips/kvm/trap_emul.c | 3 +++ arch/mips/kvm/vz.c| 3 +++ 4

[PATCH 04/15] KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16

Loongson-3 based machines can have as many as 16 CPUs, and so does memory slots, so increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- arch/mips/include/asm/kvm_host.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

qemu-devel@nongnu.org

rder to support variable ASID_MASK, KVM_ENTRYHI_ASID should also be changed to cpu_asid_mask(&boot_cpu_data). Cc: sta...@vger.kernel.org Signed-off-by: Xing Li [Huacai: Change current_cpu_data to boot_cpu_data for optimization] Signed-off-by: Huacai Chen --- arch/mips/include/asm/kvm_host.

[PATCH 01/15] mips: define pud_index() regardless of page table folding

.com Tested-by: Bibo Mao Tested-by: Huacai Chen Reported-by: Paolo Bonzini Signed-off-by: Mike Rapoport [Huacai: Add Tested-by and take this patch into my series, because my series can't build an available kernel if without this patch.] Signed-off-by: Huacai Chen --- arch/mips/inclu

[PATCH 0/15] KVM: MIPS: Add Loongson-3 support (Host Side)

(&boot_cpu_data) KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits Huacai Chen(12): KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16 KVM: MIPS: Add EVENTFD support which is needed by VHOST KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd KVM: MIPS: Introduce and

Re: [PATCH 3/3] MAINTAINERS: Add myself as fulong2e co-maintainer

Hi, Aleksandar, On Wed, Apr 8, 2020 at 11:30 PM Aleksandar Markovic wrote: > > 11:08 Sre, 08.04.2020. Huacai Chen је написао/ла: > > > > I submitted the MIPS/fulong2e support about ten years ago, and after > > that I became a MIPS kernel developer. Last year, Philippe

[PATCH 3/3] MAINTAINERS: Add myself as fulong2e co-maintainer

now (and also in future) I can have some spare time, so I can finally do some real work on QEMU/MIPS. And if possible, I hope I can be a co-maintainer of MIPS/fulong2e. Cc: Jiaxun Yang Signed-off-by: Huacai Chen --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b

[PATCH 1/3] target/mips: Support variable page size

Traditionally, MIPS use 4KB page size, but Loongson prefer 16KB page size in system emulator. So, let's define TARGET_PAGE_BITS_VARY and TARGET_PAGE_BITS_MIN to support variable page size. Cc: Jiaxun Yang Signed-off-by: Huacai Chen --- target/mips/cpu-param.h | 5 + 1 file chang

[PATCH 2/3] mips/mips_fulong2e: Set preferred page size to 16KB

Loongson processor prefers 16KB page size in system emulator, so let's define mc->minimum_page_bits to 14. Cc: Jiaxun Yang Signed-off-by: Huacai Chen --- hw/mips/mips_fulong2e.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index

Re: [PATCH] target/mips: Fix loongson multimedia condition instructions

;Can you refer to the datasheet in the commit message, or have someone > >>from Loongson Technology, Lemote Tech or with access to the specs ack > >>your patch? > > > >I just confirmed with Loongson guys on IM. > > > >+ Huacai > > +Huaca

[Qemu-devel] [PATCH] Remove incorrect pci_mem_base setting in bonito northbridge

This mistake makes PCI devices can't work correctly. Signed-off-by: Huacai Chen --- hw/bonito.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/hw/bonito.c b/hw/bonito.c index 8b81032..dcf0311 100644 --- a/hw/bonito.c +++ b/hw/bonito.c @@ -775,7 +775,6 @@ P

[Qemu-devel] [RFC][PATCH] PCI: fix pci_to_cpu_addr() issue

to 0, PMON can't work, but if set pci_mem_base to 0x1000, Linux can't access PCI. So I make this patch to make both cases works. However, I don't know whether the modification will break other archs, so request for comments here. Signed-off-by: Huacai Chen --- hw/pci.c |

[Qemu-devel] [PATCH v6 3/6] MIPS: Initial support of VIA IDE controller used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.objs|1 + default-configs/mips64el-softmmu.mak |1 + hw/ide.h |1 + hw/ide/via.c | 191 ++ 4 files changed, 194 insertions(+), 0

[Qemu-devel] [PATCH v6 6/6] MIPS: Initial support of fulong mini pc (machine construction)

Signed-off-by: Huacai Chen --- Makefile.target|2 +- hw/mips_fulong2e.c | 416 2 files changed, 417 insertions(+), 1 deletions(-) create mode 100644 hw/mips_fulong2e.c diff --git a/Makefile.target b/Makefile.target index caabacd

[Qemu-devel] [PATCH v6 1/6] MIPS: Initial support of bonito north bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |1 + default-configs/mips64el-softmmu.mak |1 + hw/bonito.c | 809 ++ hw/mips.h|3 + 4 files changed, 814 insertions(+), 0

[Qemu-devel] [PATCH v6 5/6] MIPS: Initial support of fulong mini pc (CPU definition)

Signed-off-by: Huacai Chen --- target-mips/mips-defs.h |4 target-mips/translate_init.c | 35 +++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index a7f4697..bf094a3 100644 --- a

[Qemu-devel] [PATCH v6 4/6] MIPS: Initial support of VIA USB controller used by fulong mini pc

Signed-off-by: Huacai Chen --- hw/usb-uhci.c | 28 hw/usb-uhci.h |1 + 2 files changed, 29 insertions(+), 0 deletions(-) diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 624d55b..3eb9832 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1152,6 +1152,24

[Qemu-devel] [PATCH v6 2/6] Initial support of vt82686b south bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |2 +- hw/pci_ids.h|8 + hw/vt82c686.c | 597 +++ hw/vt82c686.h | 11 + 4 files changed, 617 insertions(+), 1 deletions(-) create mode 100644 hw/vt82c686.c create mode 100644

[Qemu-devel] [PATCH v5 6/6] MIPS: Initial support of fulong mini pc (machine construction)

Signed-off-by: Huacai Chen --- Makefile.target|2 +- hw/mips_fulong2e.c | 416 2 files changed, 417 insertions(+), 1 deletions(-) create mode 100644 hw/mips_fulong2e.c diff --git a/Makefile.target b/Makefile.target index 4b23e6d

[Qemu-devel] [PATCH v5 5/6] MIPS: Initial support of fulong mini pc (CPU definition)

Signed-off-by: Huacai Chen --- target-mips/mips-defs.h |4 target-mips/translate_init.c | 35 +++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index a7f4697..bf094a3 100644 --- a

[Qemu-devel] [PATCH v5 3/6] MIPS: Initial support of VIA IDE controller used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.objs|1 + default-configs/mips64el-softmmu.mak |1 + hw/ide.h |1 + hw/ide/via.c | 191 ++ 4 files changed, 194 insertions(+), 0

[Qemu-devel] [PATCH v5 2/6] MIPS: Initial support of vt82686b south bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |2 +- hw/pci_ids.h|8 + hw/vt82c686.c | 569 +++ hw/vt82c686.h | 11 + 4 files changed, 589 insertions(+), 1 deletions(-) create mode 100644 hw/vt82c686.c create mode 100644

[Qemu-devel] [PATCH v5 4/6] MIPS: Initial support of VIA USB controller used by fulong mini pc

Signed-off-by: Huacai Chen --- hw/usb-uhci.c | 29 + hw/usb-uhci.h |1 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 624d55b..accfe2e 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1149,6 +1149,25

[Qemu-devel] [PATCH v5 1/6] MIPS: Initial support of bonito north bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |1 + default-configs/mips64el-softmmu.mak |1 + hw/bonito.c | 809 ++ hw/mips.h|3 + 4 files changed, 814 insertions(+), 0

[Qemu-devel] [PATCH v4 5/7] MIPS: Initial support of fulong mini pc (CPU definition)

Signed-off-by: Huacai Chen --- target-mips/mips-defs.h |4 target-mips/translate_init.c | 35 +++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index c57de02..38594da 100644 --- a

[Qemu-devel] [PATCH v4 2/7] MIPS: Initial support of vt82686b south bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |2 +- hw/pci_ids.h|8 + hw/vt82c686.c | 567 +++ hw/vt82c686.h | 11 + 4 files changed, 587 insertions(+), 1 deletions(-) create mode 100644 hw/vt82c686.c create mode 100644

[Qemu-devel] [PATCH v4 6/7] MIPS: Initial support of fulong mini pc (machine construction)

Signed-off-by: Huacai Chen --- Makefile.target|2 +- hw/mips_fulong2e.c | 402 2 files changed, 403 insertions(+), 1 deletions(-) create mode 100644 hw/mips_fulong2e.c diff --git a/Makefile.target b/Makefile.target index 92ba282

[Qemu-devel] [PATCH v4 4/7] MIPS: Initial support of VIA USB controller used by fulong mini pc

Signed-off-by: Huacai Chen --- hw/usb-uhci.c | 29 + hw/usb-uhci.h |1 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 624d55b..91d827e 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1149,6 +1149,25

[Qemu-devel] [PATCH v4 3/7] MIPS: Initial support of VIA IDE controller used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.objs|1 + default-configs/mips64el-softmmu.mak |1 + hw/ide.h |1 + hw/ide/via.c | 191 ++ 4 files changed, 194 insertions(+), 0

[Qemu-devel] [PATCH v4 1/7] MIPS: Initial support of bonito north bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |1 + default-configs/mips64el-softmmu.mak |1 + hw/bonito.c | 808 ++ hw/mips.h|3 + 4 files changed, 813 insertions(+), 0

[Qemu-devel] [PATCH v3 1/7] MIPS: Initial support of bonito north bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |1 + default-configs/mips64el-softmmu.mak |1 + hw/bonito.c | 816 ++ hw/mips.h|3 + 4 files changed, 821 insertions(+), 0

[Qemu-devel] [PATCH v3 3/7] MIPS: Initial support of VIA IDE controller used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.objs|1 + default-configs/mips64el-softmmu.mak |1 + hw/ide.h |1 + hw/ide/via.c | 176 ++ 4 files changed, 179 insertions(+), 0

[Qemu-devel] [PATCH v3 6/7] MIPS: Initial support of fulong mini pc (machine construction)

Signed-off-by: Huacai Chen --- Makefile.target|2 +- hw/mips_fulong2e.c | 402 2 files changed, 403 insertions(+), 1 deletions(-) create mode 100644 hw/mips_fulong2e.c diff --git a/Makefile.target b/Makefile.target index 92ba282

[Qemu-devel] [PATCH v3 5/7] MIPS: Initial support of fulong mini pc (CPU definition)

Signed-off-by: Huacai Chen --- target-mips/mips-defs.h |4 target-mips/translate_init.c | 35 +++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index c57de02..38594da 100644 --- a

[Qemu-devel] [PATCH v3 4/7] MIPS: Initial support of VIA USB controller used by fulong mini pc

Signed-off-by: Huacai Chen --- hw/usb-uhci.c | 20 hw/usb-uhci.h |1 + 2 files changed, 21 insertions(+), 0 deletions(-) diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 624d55b..feb44e6 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1152,6 +1152,16 @@ static int

[Qemu-devel] [PATCH v3 2/7] MIPS: Initial support of vt82686b south bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |2 +- hw/pci_ids.h|8 + hw/vt82c686.c | 579 +++ hw/vt82c686.h | 11 + 4 files changed, 599 insertions(+), 1 deletions(-) create mode 100644 hw/vt82c686.c create mode 100644

[Qemu-devel] [PATCH v2 5/6] MIPS: Initial support of fulong mini pc (CPU definition, machine construction, etc.)

Signed-off-by: Huacai Chen --- Makefile.target |2 +- hw/mips_fulong2e.c | 421 ++ target-mips/translate_init.c | 35 3 files changed, 457 insertions(+), 1 deletions(-) create mode 100644 hw/mips_fulong2e.c diff --git a

[Qemu-devel] [PATCH v2 4/6] MIPS: Initial support of VIA USB controller used by fulong mini pc

Signed-off-by: Huacai Chen --- hw/usb-uhci.c | 30 ++ hw/usb-uhci.h |1 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 624d55b..5fd5388 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1152,6 +1152,26

[Qemu-devel] [PATCH v2 3/6] MIPS: Initial support of VIA IDE controller used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.objs|1 + default-configs/mips64el-softmmu.mak |1 + hw/ide.h |1 + hw/ide/via.c | 185 ++ 4 files changed, 188 insertions(+), 0

[Qemu-devel] [PATCH v2 2/6] MIPS: Initial support of vt82686b south bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |2 +- hw/pc.h |7 + hw/pci_ids.h|8 + hw/vt82c686.c | 786 +++ 4 files changed, 802 insertions(+), 1 deletions(-) create mode 100644 hw/vt82c686.c diff --git a

[Qemu-devel] [PATCH v2 1/6] MIPS: Initial support of bonito north bridge used by fulong mini pc

Signed-off-by: Huacai Chen --- Makefile.target |1 + default-configs/mips64el-softmmu.mak |1 + hw/bonito.c | 950 ++ hw/mips.h|3 + 4 files changed, 955 insertions(+), 0

[Qemu-devel] [PATCH resend 3/6] MIPS: Initial support of VIA IDE controller used by fulong mini pc

resend by git send-email to avoid line-wrapping Signed-off-by: Huacai Chen --- Makefile.objs|1 + default-configs/mips64el-softmmu.mak |1 + hw/ide.h |1 + hw/ide/via.c | 185

[Qemu-devel] [PATCH resend 1/6] MIPS: Initial support of bonito north bridge used by fulong mini pc

resend by git send-email to avoid line-wrapping Signed-off-by: Huacai Chen --- Makefile.target |1 + default-configs/mips64el-softmmu.mak |1 + hw/bonito.c | 950 ++ hw/mips.h

[Qemu-devel] [PATCH resend 4/6] MIPS: Initial support of VIA USB controller used by fulong mini pc

resend by git send-email to avoid line-wrapping Signed-off-by: Huacai Chen --- hw/usb-uhci.c | 30 ++ hw/usb-uhci.h |1 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 624d55b..5fd5388 100644 --- a/hw/usb

[Qemu-devel] [PATCH resend 5/6] MIPS: Initial support of fulong mini pc (CPU definition, machine construction, etc.)

resend by git send-email to avoid line-wrapping Signed-off-by: Huacai Chen --- Makefile.target |2 +- hw/mips_fulong2e.c | 420 ++ target-mips/translate_init.c | 35 3 files changed, 456 insertions(+), 1 deletions

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