tion masked_msbs != 0 && masked_msbs != mask is not
fulfilled
and the check passes.
Signed-off-by: Irina Ryapolova
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
Changes for v2:
-Add more detailed commit message
Changes for v3:
-rebase the patch on
https://github.com/
address bits 63:59 must all be zeros, or else a guest-page-fault
exception occurs.
Signed-off-by: Irina Ryapolova
---
target/riscv/cpu_helper.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index
tion masked_msbs != 0 && masked_msbs != mask is not
fulfilled
and the check passes.
Signed-off-by: Irina Ryapolova
---
Changes for v2:
-Add more detailed commit message
---
target/riscv/cpu_helper.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(
Added xATP_MODE validation for vsatp/hgatp CSRs.
The xATP register is an SXLEN-bit read/write WARL register, so
the legal value must be returned (See riscv-privileged-20211203,
SATP/VSATP/HGATP CSRs).
Signed-off-by: Irina Ryapolova
---
target/riscv/csr.c | 52
trying to write to SATP CSR val = 0x1000
(SATP_MODE = 1 - Reserved for standard use)
and after that we are trying to read SATP_CSR. We read from the SATP CSR value
= 0x1000, which is not a correct
operation (return illegal value).
Signed-off-by: Irina Ryapolova
---
target
Added xATP_MODE validation for vsatp/hgatp CSRs.
The xATP register is an SXLEN-bit read/write WARL register, so
the legal value must be returned (See riscv-privileged-20211203,
SATP/VSATP/HGATP CSRs).
Signed-off-by: Irina Ryapolova
---
target/riscv/csr.c | 52
correct
operation (return illegal value).
Signed-off-by: Irina Ryapolova
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fde7ce1a53..735fb27be7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
at VS level)
Signed-off-by: Irina Ryapolova
---
Changes for v2:
-added more information in commit message
---
target/riscv/csr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..0c21145eaf 100644
--- a/target/riscv
From: Vadim Shakirov
In the AIA specification in the paragraph "Virtual interrupts for VS level"
it is indicated for interrupts 13-63: if the bit in hideleg is enabled,
then the corresponding vsip and vsie bits are aliases to sip and sie
Signed-off-by: Vadim Shakirov
Reviewed-by: Alistair Franc
Need to convert mmu_idx to privilege mode for PMP function.
Signed-off-by: Irina Ryapolova
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ce7322011d..fc090d729a 100644
--- a/target
trying to write to SATP CSR val = 0x1000
(SATP_MODE = 1 - Reserved for standard use)
and after that we are trying to read SATP_CSR. We read from the SATP CSR value
= 0x1000, which is not a correct
operation (return illegal value).
Signed-off-by: Irina Ryapolova
Reviewed-by
Added xATP_MODE validation for vsatp/hgatp CSRs.
The xATP register is an SXLEN-bit read/write WARL register, so
the legal value must be returned (See riscv-privileged-20211203,
SATP/VSATP/HGATP CSRs).
Signed-off-by: Irina Ryapolova
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/csr.c
)
Signed-off-by: Irina Ryapolova
---
target/riscv/csr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..0c21145eaf 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3585,6 +3585,21 @@ static int read_hvictl
From: Vadim Shakirov
In the AIA specification in the paragraph "Virtual interrupts for VS level"
it is indicated for interrupts 13-63: if the bit in hideleg is enabled,
then the corresponding vsip and vsie bits are aliases to sip and sie
Signed-off-by: Vadim Shakirov
---
target/riscv/csr.c | 2
)
Signed-off-by: Irina Ryapolova
---
target/riscv/csr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..0c21145eaf 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3585,6 +3585,21 @@ static int read_hvictl
From: Vadim Shakirov
In the AIA specification in the paragraph "Virtual interrupts for VS level"
it is indicated for interrupts 13-63: if the bit in hideleg is enabled,
then the corresponding vsip and vsie bits are aliases to sip and sie
Signed-off-by: Vadim Shakirov
---
target/riscv/csr.c | 2
Need to convert mmu_idx to privilege mode for PMP function.
Signed-off-by: Irina Ryapolova
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ce7322011d..fc090d729a 100644
--- a/target
From: Vadim Shakirov
In the AIA specification in the paragraph "Virtual interrupts for VS level"
it is indicated for interrupts 13-63: if the bit in hideleg is enabled,
then the corresponding vsip and vsie bits are aliases to sip and sie
Signed-off-by: Vadim Shakirov
Reviewed-by: Alistair Franc
at VS level)
Signed-off-by: Irina Ryapolova
---
Changes for v2:
-added more information in commit message
Changes for v3:
-applied patch in master
---
target/riscv/csr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index
After exit Qemu need to return the terminal to the default state.
Signed-off-by: Irina Ryapolova
---
chardev/char-win-stdio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/chardev/char-win-stdio.c b/chardev/char-win-stdio.c
index 1a18999e78..4fa2c3de8b 100644
--- a/chardev/char-win
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