GPIO 1.8v, removes
ASPEED_DEV_GPIO_1_8V. It is enough to only have ASPEED_DEV_GPIO
device in AST2700.
The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at
bit 18. Therefore, correct GPIO irq 130.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c
operation for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 380 ++
1 file changed, 380 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
;pending == 1
set->int_status == 0b10
Signed-off-by: Jamin Lin
Suggested-by: Andrew Jeffery
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base
address is start at 0x14C0_B000 and its address space is 0x1000.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw
_gpio-test test failed if arch is arm
> v6: Add to test aspeed_gpio-test for aarch64
> v7: Move GPIO testcase for AST2700 to ast2700-gpio-test.c
>
> Jamin Lin (8):
> hw/gpio/aspeed: Fix coding style
> hw/gpio/aspeed: Support to set the different memory size
> hw/gpio/aspe
input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le
Add GPIO test cases to test output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/ast2700-gpio-test.c | 95 +
tests/qtest/meson.build | 3 ++
2 files changed, 98 insertions(+)
create mode 100644 tests/qtest/ast2700
test aspeed_gpio-test for aarch64
v7: Move GPIO testcase for AST2700 to ast2700-gpio-test.c
Jamin Lin (8):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Fix clear incorrect interrupt
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 7 ++-
include/hw/gpio/aspeed_gpio.h | 1 +
2 files changed, 7 insertions
Hi Thomas, Cedric
> Subject: Re: [PATCH v6 8/8] hw/gpio/aspeed: Add test case for AST2700
>
> On 30/09/2024 18.48, Cédric Le Goater wrote:
> > On 9/30/24 18:36, Thomas Huth wrote:
> >> On 30/09/2024 10.52, Jamin Lin wrote:
> >>> Add test case to test GPIO out
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base
address is start at 0x14C0_B000 and its address space is 0x1000.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm
;pending == 1
set->int_status == 0b10
Signed-off-by: Jamin Lin
Suggested-by: Andrew Jeffery
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
test aspeed_gpio-test for aarch64
Jamin Lin (8):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index
mode
hw/gpio/aspeed: Add
operation for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 380 ++
1 file changed, 380 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 77 --
tests/qtest/meson.build| 3 ++
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/tests/qtest
input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 7 ++-
include/hw/gpio/aspeed_gpio.h | 1 +
2 files changed, 7 insertions
GPIO 1.8v, removes
ASPEED_DEV_GPIO_1_8V. It is enough to only have ASPEED_DEV_GPIO
device in AST2700.
The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at
bit 18. Therefore, correct GPIO irq 130.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 5 ++---
1 file changed, 2
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
Hi Konstantin
> Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700
>
> On Fri, Sep 27, 2024 at 06:29:22AM GMT, Jamin Lin wrote:
> > > Also, your emails have an invalid "From" field set to
> > > "qemu-devel@nongnu.org" when retrieved with the b4
Hi Thomas,
> Subject: Re: [PATCH v5 7/7] hw/gpio/aspeed: Add test case for AST2700
>
> On 27/09/2024 10.33, Jamin Lin wrote:
> > Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
> >
> > Signed-off-by: Jamin Lin
> > ---
> >
Hi Cedric,
> Subject: Re: [PATCH v5 6/7] aspeed/soc: Support GPIO for AST2700 and correct
> irq 130
>
> Hello Jamin,
>
> On 9/27/24 10:33, Jamin Lin wrote:
> > The register set of GPIO have a significant change since AST2700.
> > Each GPIO pin has their own individ
input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le
;pending == 1
set->int_status == 0b10
Signed-off-by: Jamin Lin
Suggested-by: Andrew Jeffery
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 7 ++-
include/hw/gpio/aspeed_gpio.h | 1 +
2 files changed, 7 insertions
GICINT130_INTC at
bit 18. Therefore, correct GPIO irq 130.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 761ee11657..dca660eb6b 100644
--- a/hw/arm
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 68 ++
1 file changed, 68 insertions(+)
diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c
index
operation for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 380 ++
1 file changed, 380 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
v4: add test cases to test GPIO for AST2700 and update commit messages
v5: fix aspeed_gpio-test test failed if arch is arm
Jamin Lin (7
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
Hi Cedric,
> Subject: [PATCH v4 7/7] hw/gpio/aspeed: Add test case for AST2700
>
> Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
>
> Signed-off-by: Jamin Lin
> ---
> tests/qtest/aspeed_gpio-test.c | 64 ++
input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
v4: add test cases to test GPIO for AST2700 and update commit messages
Jamin Lin (7):
hw/gpio/aspeed: Fix coding style
hw/gpio
GICINT130_INTC at
bit 18. Therefore, correct GPIO irq 130.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 761ee11657..dca660eb6b 100644
--- a/hw/arm
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 7 ++-
include/hw/gpio/aspeed_gpio.h | 1 +
2 files changed, 7 insertions
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 64 ++
1 file changed, 64 insertions(+)
diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c
index
operation for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 380 ++
1 file changed, 380 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
;pending == 1
set->int_status == 0b10
Signed-off-by: Jamin Lin
Suggested-by: Andrew Jeffery
Reviewed-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
Hi Cedric,
> Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700
>
> Hello Jamin,
>
> >> Could you please to add tests in tests/qtest/aspeed_gpio-test.c for
> >> this changes ? At least one with the ast2700-evb machine if possible.
> >>
> >
> > Will add
> Thanks for the effort. I appreciate.
>
Hi Andrew,
>
> On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote:
> > AST2700 integrates two set of Parallel GPIO Controller with maximum
> > 212 control pins, which are 27 groups.
> > (H, exclude pin: H7 H6 H5 H4)
> >
> > In the previous design of A
Hi Cedric,
> Subject: Re: [PATCH v3 6/6] aspeed/soc: Support GPIO for AST2700
>
> On 9/26/24 09:45, Jamin Lin wrote:
> > Add GPIO model for AST2700 GPIO support.
> > The GPIO controller registers base address is start at
> > 0x14C0_B000 and its address space is 0x100
Hi Cedric,
> Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700
>
> Hello Jamin,
>
> On 9/26/24 09:45, Jamin Lin wrote:
> > v1: Support GPIO for AST2700
> > v2: Fix clear incorrect interrupt status and adds reviewer suggestions
> > v3: remove nested condition
Hi Andres,
> Subject: Re: [PATCH v3 4/6] hw/gpio/aspeed: Fix clear incorrect interrupt
> status
> for GPIO index mode
>
> On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote:
> > The interrupt status field is W1C, where a set bit on read indicates
> > an inter
Add GPIO model for AST2700 GPIO support.
The GPIO controller registers base address is start at
0x14C0_B000 and its address space is 0x1000.
The AST2700 GPIO controller interrupt is connected to
GICINT130_INTC at bit 18.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 18
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 7 ++-
include/hw/gpio/aspeed_gpio.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a
for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 380 ++
1 file changed, 380 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 16c18ea2f7..a5b3f454e8 100644
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 71756664dd..00fb72a509
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
Jamin Lin (6):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support
input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin
---
hw/gpio/aspee
= 1
s->pending == 1
set->int_status == 0b10
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 8725606aec..16c18ea2f7 100644
--- a/hw/gpio/aspeed
Hi Andres,
> Subject: Re: [PATCH v2 4/6] hw/gpio/aspeed: Fix clear incorrect interrupt
> status
> for GPIO index mode
>
> Hi Jamin,
>
> On Wed, 2024-09-25 at 11:34 +0800, Jamin Lin wrote:
> > The interrupt status field is W1C, where a set bit on read indicates
>
Hi Andrew,
> Subject: Re: [PATCH v2 5/6] hw/gpio/aspeed: Add AST2700 support
>
> On Wed, 2024-09-25 at 11:34 +0800, Jamin Lin wrote:
> >
> > +/* interrupt status */
> > +if (SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)) {
> > +pending = extr
for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 375 ++
1 file changed, 375 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 58ae63e3c1..e09e34ff2d 100644
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 7 ++-
include/hw/gpio/aspeed_gpio.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a
Add GPIO model for AST2700 GPIO support.
The GPIO controller registers base address is start at
0x14C0_B000 and its address space is 0x1000.
The AST2700 GPIO controller interrupt is connected to
GICINT130_INTC at bit 18.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 18
t;pending = 1
set->int_status == 0b10
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 6e6ab48b56..58ae63e3c1 100644
--- a/hw/gpio/aspeed_gpio.c
++
input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin
---
hw/gpio/aspee
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 5 +++--
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 71756664dd..a5886ffa43 100644
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestion
Jamin Lin (6):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Fix clear
Hi Andrew,
> Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
>
> On Tue, 2024-09-24 at 03:03 +0000, Jamin Lin wrote:
> > Hi Andrew,
> >
> > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> > >
> > > Hi Jamin,
> >
Hi Andrew,
> Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
>
> On Tue, 2024-09-24 at 06:48 +0000, Jamin Lin wrote:
> > Hi Andrew,
> >
> > > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> > >
> > > Hi Andrew,
>
Hi Andrew,
> Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
>
> Hi Andrew,
>
> > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> >
> > Hi Jamin,
> >
> > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote:
> > > AST
Hi Andrew,
> Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
>
> Hi Jamin,
>
> On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote:
> > AST2700 integrates two set of Parallel GPIO Controller with maximum
> > 212 control pins, which are 27 groups.
>
Hi Cedric,
> Subject: RE: [SPAM] [PATCH v3 00/11] support I2C for AST2700
>
> Hi Cedric,
>
> > Subject: Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700
> >
> > Hello Jamin,
> >
> > > Just want you to know that I and Troy are working on the following
> > > tasks for
> > AST2700.
> > > 1. Supp
Add GPIO model for AST2700 GPIO support.
The GPIO controller registers base address is start at
0x14C0_B000 and its address space is 0x1000.
The AST2700 GPIO controller interrupt is connected to
GICINT130_INTC at bit 18.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 18
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 3 ++-
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 71756664dd..901b576144 100644
v1: support GPIO for AST2700
Jamin Lin (5):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Add AST2700 support
aspeed/soc: Support GPIO for AST2700
hw/arm/aspeed_ast27x0.c
input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin
---
hw/gpio/aspee
for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 373 ++
1 file changed, 373 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index f23ffae34d..e3d5556dc1 100644
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 7 ++-
include/hw/gpio/aspeed_gpio.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a
Hi Cedric,
> Subject: Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700
>
> Hello Jamin,
>
> > Just want you to know that I and Troy are working on the following tasks for
> AST2700.
> > 1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35)
>
> Oh nice. This is a good topic for
Hi Cedric,
> Subject: Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700
>
> On 9/3/24 10:35, Jamin Lin wrote:
> > v1:
> > - support I2C for AST2700
> >
> > v2:
> > - fix review issues and add reviewer suggestion
> > - update avocado test ca
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index c0b01e8f1f
pin
if users only provide the device id with its bus number index.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 4257b5e8af..a5eb78524f 100644
--- a/hw/arm
GICINT130_INTC at bit 0.
I2C bus 15 is connected to GICINT130_INTC at bit 15.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index a5eb78524f..761ee11657 100644
--- a
al
high part address for DMA operation.
(high part physical address bit[7:0] – 4)
Signed-off-by: Jamin Lin
---
hw/i2c/aspeed_i2c.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index c1ff80b1cf..44c3c39233 100644
--- a/hw/i2c/aspeed
Introduce a new class attribute to make user set each I2C bus gap size.
Update formula to create all I2C bus register memory regions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 3 ++-
include/hw/i2c/aspeed_i2c.h | 1 +
2 files changed, 3 insertions
create either a share pool buffer or bus pool buffers
in aspeed_i2c_realize. Update each pull buffer size to 0x10 for AST2500
and 0x20 for AST2600 and AST1030.
Incrementing the version of aspeed_i2c_bus_vmstate to 6.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c
sponds the bits [31:0] of the 64 bits address
of the Tx buffer address.
Introduce a new has_dma64 class attribute and new registers for the
new mode to support DMA 64 bits dram address.
Update new mode register number to 28.
The aspeed_i2c_bus_vmstate is changed again and
version is not increased bec
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 ++
1 file changed, 10 insertions(+)
diff
- 0xDBF: Device 12 buffer
0xEA0 - 0xEBF: Device 13 buffer
0xFA0 – 0xFBF: Device 14 buffer
0x10A0 – 0x10BF: Device 15 buffer
Introduce a new class attribute to make user set each I2C bus
pool buffer gap size. Update formula to create all I2C bus
pool buffer memory regions.
Signed-off-by: Jamin Lin
v1:
- support I2C for AST2700
v2:
- fix review issues and add reviewer suggestion
- update avocado test case for AST2700 I2C
- support i2c bus pool
v3:
- update commit messages and commit title
- update API to get the device irq
Jamin Lin (11):
hw/i2c/aspeed: Support discontinuous register
because it was done earlier in the same series.
Signed-off-by: Jamin Lin
---
hw/i2c/aspeed_i2c.c | 51 +++--
include/hw/i2c/aspeed_i2c.h | 9 +--
2 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i
datasheet.
An I2C controller registers owns 8KB address space.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 62 +
include/hw/i2c/aspeed_i2c.h | 1 +
2 files changed, 63 insertions(+)
diff --git a/hw/i2c/aspeed_i2c.c b
Hi Cedric,
> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for
> DMA 64 bits
>
> On 9/3/24 05:06, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram
> >&
Hi Cedric,
> Subject: Re: [PATCH v2 08/11] aspeed/soc: introduce a new API to get the INTC
> orgate information
>
> Jamin,
>
> On 8/8/24 04:49, Jamin Lin wrote:
> > Currently, users can set the intc mapping table with enumerated device
> > id and device irq to
33 and 32.
Thanks-Jamin
>
> On 8/8/24 04:49, Jamin Lin wrote:
> > ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the
> > base address of dram is "0x4 " which is 64bits address.
> >
> > The AST2700 support the maximum DRAM size is 8 GB.
its address
>
> So more proposals to improve the commit log below,
>
> On 8/8/24 04:49, Jamin Lin wrote:
> > ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the
> > base address of dram is "0x4 " which
>
> and
>
> > is 64bi
ll commit title to use a capital letter on the first word
in the next patch series(v3)
> hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in
> AspeedI2Cbus
>
> On 8/8/24 04:49, Jamin Lin wrote:
> > The "Current DMA Operating Address Status(0x50)" register of I2
ion pointer need to be discussion.
Jamin Lin (11):
hw/i2c/aspeed: support discontinuous register memory region of I2C bus
hw/i2c/aspeed: introduce a new bus pool buffer attribute in
AspeedI2Cbus
hw/i2c/aspeed: support discontinuous poll buffer memory region of I2C
bus
hw/i2c/asp
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 ++
1 file changed, 10 insertions(+)
diff
GICINT130_INTC at bit 0.
I2C bus 15 is connected to GICINT130_INTC at bit 15.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 0bbd66110b..e84141c13b 100644
source bit number
if users only provide the start bus number of device.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 4257b5e8af..0bbd66110b 100644
--- a/hw
1:0] of the 64 bits address
of the Tx buffer address.
Introduce a new has_dma64 class attribute and new registers of
new mode to support DMA 64 bits dram address.
Update new mode register number to 28.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 48 +
2CD24 old mode)" and
"DMA Operating Address Status (I2CC50 new mode)" are used for showing the
low part dram offset bits [31:0], so change to read/write both register bits
[31:0] in
bus register read/write functions.
Signed-off-by: Jamin Lin
---
hw/i2c/aspeed_i2c.c | 51 ++
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index f8e263d37e..6935f5f57c 100644
--- a/tests
al
high part address for DMA operation.
(high part physical address bit[7:0] – 4)
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index c1ff80b1cf..44c3c3
Introduce a new class attribute to make user set each I2C bus gap size.
Update formula to create all I2C bus register memory regions.
Signed-off-by: Jamin Lin
---
hw/i2c/aspeed_i2c.c | 3 ++-
include/hw/i2c/aspeed_i2c.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a
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