Yes, both the comment and enum should be updated.
-Original Message-
From: Aleksandar Markovic
Sent: Thursday, December 27, 2018 2:23 PM
To: Janeczek, Craig ; Stefan Markovic
; Aleksandar Markovic ;
qemu-devel@nongnu.org
Subject: Re: [PATCH 1/6] target/mips: MXU: Add missing
Yes built a binary testing these instructions and ran it against HW along with
a qemu binary with your patches. The opcodes align with what I mentioned in the
email.
-Original Message-
From: Aleksandar Markovic
Sent: Thursday, December 27, 2018 1:44 PM
To: Janeczek, Craig ; Stefan
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add translation handlers for max/min MXU instructions.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 356 +---
> 1 file changed, 335 insertions(+), 21
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU, and
> LXHU instructions. They were for some reason forgotten in previous
> commits. The MXU opcode list and decoding engine should be now
> complete.
I plan on getting back to this development effort next week.
-Original Message-
From: Aleksandar Markovic
Sent: Wednesday, September 5, 2018 9:36 AM
To: Janeczek, Craig ; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net
Subject: Re: [PATCH v4 0/9] Add limited MXU instruction support
>
It is possible but due to the non-uniform nature of the bit fields which
indicate the instructions the mask used might end up being instruction
specific. This would lead to a tiered approach where the current enum would be
the top level, then each group under there might have its own enum, mask
To clarify the OPC_MUL here is not an MXU instruction, this is the original
OPC_MUL that was in the special2 instruction set. The inclusion of this
instruction in this switch statement is due to the suggested method of
splitting up the mxu commands instruction handling switch statement from the
That seems like a good plan to separate these tasks. I will implement this in
the next patchset. Thank you
-Original Message-
From: Aleksandar Markovic
Sent: Thursday, August 30, 2018 8:40 AM
To: Janeczek, Craig ; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; Petar Jovanovic ;
To clarify, if MXU is present (a cpu defined to have MXU instructions is
selected) we will never run any of the other special2 commands? That would
actually simplify the implementation.
Also I understand the want for clean code, I appreciate the comments.
-Original Message-
From:
I will re-work each of the mxu_gen_ functions to check for MXUEN and jump
over the implementation of the instruction if not enabled.
I would like to clarify the structure of the switch statement before
implementing it.
I was originally planning on checking if there was a MXU hit and MXUEN was
The only commands that have the 5th bit required to address XR16 are
S32M2I/S32I2M.
I can split it out into a separate utility function and put a conditional into
the S32M2I/S32I2M functions if you are more comfortable with that.
-Original Message-
From: Aleksandar Markovic
Sent:
What happens if reg > 16? Also, the argument reg should be unsigned.
If rev > 16 the instruction is invalid. What type of error can/should I throw
here.
This does not handle the case xra == XR16. From the doc:
I do not see where the case is un-handled. XR16 maps to index 15 in the mxu_gpr
I see that I can check the loongson instructions by checking for
INSN_LOONGSON2F. Using MXU if that is not set
What should I check for the mult or misc instructions that were there first?
-Original Message-
From: Aleksandar Markovic
Sent: Tuesday, August 28, 2018 11:07 AM
To:
Where is the definition of MXU control register (MXU_CR)?
MXU_CR is the last element in this array.
Before sending patches, it is obligatory to run scripts/checkpatch.pl
- this (missing braces) will be reported by this script.
I did run checkpath before sending a patch. This was not reported.
https://github.com/MIPS/CI20_mplayer/blob/ci20_mplayer/mxu_as
Sorry I mis-read our comment. The bit layouts were pulled from this script and
validated by visually examining compiled code.
-Original Message-
From: Janeczek, Craig
Sent: Monday, August 27, 2018 8:15 AM
To: 'Richard
https://www.rockbox.org/wiki/pub/Main/IngenicJz4760B/jz-simd-docs.pdf
I pulled them from here. I also wrote a series of tests which I cross compiled
then ran on both HW and through QEMU. Although I did not submit those tests as
part of this patchset as I am unsure of how to add them into the
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