Detected by asm test suite failures in dav1d
(https://code.videolan.org/videolan/dav1d). Can be reproduced by
`qemu-x86_64 -cpu core2duo ./tests/checkasm --test=mc_8bpc 1659890620`.
Signed-off-by: Janne Grunau
---
target/i386/ops_sse.h | 53 +++
1 file
On 2014-04-16 11:59:58 +0100, Peter Maydell wrote:
On 16 April 2014 11:55, Alex Bennée alex.ben...@linaro.org wrote:
Peter Maydell peter.mayd...@linaro.org writes:
Can you attach a statically linked test case binary, please?
I can reproduce with the source file. It looks like:
@@
On 2014-03-09 15:10:57 +, Peter Maydell wrote:
From: Alex Bennée alex.ben...@linaro.org
This implements a the remaining [US][R]SHR[R][2] opcodes which are
there is an extra 'a' and the instructions are [US][Q][R]SHR[U][N][2].
The last '[R]' is at least clearly wrong.
The commit itself
On 2014-03-06 11:40:47 +, Alex Bennée wrote:
Janne Grunau j...@jannau.net writes:
On 2014-02-25 15:54:37 +, Alex Bennée wrote:
snip
Have you got the log file unsupported line? I seem to recall you did
ping me but maybe it was just on IRC? I just want to make sure I
do
On 2014-02-25 15:54:37 +, Alex Bennée wrote:
Feedback I'm interested in
==
* Any instruction failure (please include the log line with the
unsupported message)
Neon support is not complete enough to run the hand written neon
assembler optimizations in
Hi,
On 2014-02-17 13:40:00 +, Alex Bennée wrote:
After a solid few months of work the QEMU master branch [1] has now reached
instruction feature parity with the suse-1.6 [6] tree that a lot of people
have been using to build various aarch64 binaries. In addition to the
SUSE work we have
Signed-off-by: Janne Grunau j...@jannau.net
---
linux-user/main.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index cabc9e1..9192977 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -953,7 +953,8 @@ static int
On 2013-11-20 15:47:18 +0100, Michael Matz wrote:
Hi,
On Tue, 19 Nov 2013, Janne Grunau wrote:
+static void handle_fpfpconv(DisasContext *s, uint32_t insn)
+{
+int opcode = get_bits(insn, 16, 3);
+int rmode = get_bits(insn, 20, 2);
rmode is at 19
+case 0x1
On 2013-09-27 02:48:17 +0200, Alexander Graf wrote:
This patch adds support for the AdvSIMD modified immediate group with
all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 129
On 2013-09-27 02:48:44 +0200, Alexander Graf wrote:
This patch adds emulation for the instruction group labeled
Floating-point - fixed-point conversions in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).
Signed-off-by: Alexander Graf
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