s an excellent idea.
>
> However I am still curious to _why_ it has to be done in the first place.
The display part of the GPU is partly on the PCH, and it's possible to
mix & match them a bit, so we have this detection code to figure things
out. In some cases, the PCH display portion may not even be present,
so we look for that too.
Practically speaking, we could probably assume specific CPU/PCH combos,
as I don't think they're generally mixed across generations, though SNB
and IVB did have compatible sockets, so there is the possibility of
mixing CPT and PPT PCHs, but those are register identical as far as the
graphics driver is concerned, so even that should be safe.
Beyond that, the other MCH data we need to look at is mirrored into the
GPU's MMIO space on current gens. On older gens, we do need to poke at
the memory controller a bit to get some info (see
intel_setup_mchbar()), but that's not true of newer stuff. Looks like
we only short circuit that on VLV though; we could probably do it on
SNB+.
--
Jesse Barnes, Intel Open Source Technology Center
IDGE 0x7 /* PCI/PCI-X Bridge */
> +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8/* PCI/PCI-X to PCIE Bridge */
> #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
> #define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
> #define PCI_EXP_FLAGS_SLOT 0x010
nment().
>
> Patch started as debugging effort from Cam Macdonell.
>
> Cc: Cam Macdonell
> Cc: Avi Kivity
> Cc: Jesse Barnes
> [chrisw: add iov bits]
> Signed-off-by: Chris Wright
> ---
> drivers/pci/iov.c |2 +-
> drivers/pci/pci.h |5 +++--
> 2 files chang
