Hi Anthony,
This is my OpenRISC patch queue for 2.3, it have been well tested, please pull.
Thanks to Christian and Sebastian, they made the LD/ST updated.
Regards,
Jia
The following changes since commit 16017c48547960539fcadb1f91d252124f442482:
softfloat: Clarify license status
...@macke.de
Reviwed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.h | 3 ++
target-openrisc/interrupt.c | 3 ++
target-openrisc/translate.c | 74 -
3 files changed, 79 insertions(+), 1 deletion
Macke sebast...@macke.de
Reviwed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 116
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc
On Mon, Jan 26, 2015 at 6:18 PM, Sebastian Macke sebast...@macke.de wrote:
Hi Jia,
On 1/26/2015 10:50 AM, Jia Liu wrote:
Hi Sebastian, Christian
On Sun, Jan 25, 2015 at 6:25 PM, Sebastian Macke sebast...@macke.de
wrote:
From: Christian Svensson b...@cmd.nu
This patch adds support
Hi Sebastian, Christian
On Sun, Jan 25, 2015 at 6:25 PM, Sebastian Macke sebast...@macke.de wrote:
From: Christian Svensson b...@cmd.nu
This patch adds support for atomic locks
and is an adaption from
https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
Tested via the atomic lock
));
-tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc-mem_idx, mop);
-tcg_temp_free(t0);
-}
+gen_loadstore(dc, op0, ra, rb, rd, tmp);
break;
default:
Thank you, it is good to separate the related instructions.
Reviwed-by: Jia Liu pro...@gmail.com
--
2.2.2
);
+op0 = extract32(insn, 16, 10);
Thank you for pointing this.
Acked-by: Jia Liu pro...@gmail.com
#ifdef OPENRISC_DISAS
K16 = extract32(insn, 0, 16);
#endif
--
2.2.1
Regards,
Jia
/openrisc_asim.c
new file mode 100644
index 000..80aa5ed
--- /dev/null
+++ b/hw/openrisc/openrisc_asim.c
@@ -0,0 +1,202 @@
+/*
+ * OpenRISC simulator with more peripherals
+ *
+ * Copyright (c) 2011-2014 Jia Liu pro...@gmail.com
+ * Feng Gao gf91...@gmail.com
]);
+
+
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
Acked-by: Jia Liu pro...@gmail.com
Regards,
Jia
, kernel_filename, cpu);
}
--
1.9.1
Acked-by: Jia Liu pro...@gmail.com
Regards,
Jia
[OR_TOUCHSCREEN],
cpu-env.irq[9]);
+
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
Acked-by: Jia Liu pro...@gmail.com
Regards,
Jia
Hi Richard,
Thank you!
Tested-by: Jia Liu pro...@gmail.com
On Sat, Sep 13, 2014 at 9:45 AM, Richard Henderson r...@twiddle.net wrote:
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
---
cpu-exec.c | 18 --
target-openrisc
Hi Valentin,
On Sat, Aug 23, 2014 at 1:05 AM, Valentin Manea
valentin.ma...@gmail.com wrote:
Add support for the OpenCores keyboard device to the default OpenRisc
machine.
The OpenCores keyboard device is a simple open source keyboard device
created by the OpenCores
Hi Valentin,
On Sat, Aug 23, 2014 at 1:06 AM, Valentin Manea
valentin.ma...@gmail.com wrote:
The LPC32XX is a simple MMIO touch screen device with a Linux device
driver. The device is suitable for small machines which require mouse
input but have no suitable bus(SPI, I2C).
Add the LPC32XX
Hi Valentin,
On Fri, Aug 22, 2014 at 9:10 PM, Valentin Manea
valentin.ma...@gmail.com wrote:
Add support for the OpenCores Framebuffer device and enable it by
default in the OpenRISC machine.
The OpenCores display device is a simple open source framebuffer device
created
Hi Valentin,
On Fri, Aug 22, 2014 at 9:11 PM, Valentin Manea
valentin.ma...@gmail.com wrote:
Add support for the OpenCores keyboard device to the default OpenRisc
machine.
The OpenCores keyboard device is a simple open source keyboard device
created by the OpenCores
Hi Valentin,
On Fri, Aug 22, 2014 at 9:12 PM, Valentin Manea
valentin.ma...@gmail.com wrote:
The LPC32XX is a simple MMIO touch screen device with a Linux device
driver. The device is suitable for small machines which require mouse
input but have no suitable bus(SPI, I2C).
Add the LPC32XX
Hi Valentin,
On Fri, Aug 22, 2014 at 10:01 PM, Valentin Manea
valentin.ma...@gmail.com wrote:
Hi,
I would like to share this series of patches to improve the openrisc
machine. Mostly my goal is to have the same features as the web based
machine and be able to boot qemu with exactly the
Voipio riku.voi...@iki.fi
Cc: Jia Liu pro...@gmail.com
---
linux-user/syscall.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 2eac6d5..8dbe39b 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -198,6 +198,11 @@ static
Hi Anthony,
This is my OpenRISC patch queue for 1.8, it have been well tested, please pull.
Thanks to Richard Henderson, he made the LD/ST updated.
Regards,
Jia
The following changes since commit a4550442b947d2c2b346bd2efc8fe3da16425f4d:
petalogix-ml605: Create the CPU with object_new()
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Acked-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 99 +++--
1 file changed, 32 insertions(+), 67 deletions
Hi Anthony,
Michael said he had applied the typo patch, then I waited it for days
and didn't find it in master,
so I resend the same patch in my pull request queue.
It is my fault, sorry Michael.
And, Anthony, please applied this one, please.
On Sat, Dec 14, 2013 at 4:45 PM, Jia Liu pro
ping~~
On Sat, Dec 21, 2013 at 9:47 AM, Jia Liu pro...@gmail.com wrote:
Hi Anthony,
This is my OpenRISC patch queue for 1.8, it have been well tested, please
pull.
Thanks to Richard Henderson, he made the LD/ST updated.
Thanks to Stefan Weil, he fixed a typo.
Regards,
Jia
From: Stefan Weil s...@weilnetz.de
Fix typo in comment (transaltion - translation).
And I also removed two hyphens in the same comment.
Signed-off-by: Stefan Weil s...@weilnetz.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 2
Hi Anthony,
This is my OpenRISC patch queue for 1.8, it have been well tested, please pull.
Thanks to Richard Henderson, he made the LD/ST updated.
Thanks to Stefan Weil, he fixed a typo.
Regards,
Jia
The following changes since commit f8251db121c3f051b22a7536b97d160c30bcccd4:
Merge
From: Richard Henderson r...@twiddle.net
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
Acked-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 99 +++--
1 file changed
Hi Richard,
On Thu, Dec 12, 2013 at 12:42 AM, Richard Henderson r...@twiddle.net wrote:
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-openrisc/translate.c | 99
+++--
1 file changed, 32 insertions(+), 67
translation space to execution space. */
Thank you very much!
Reviewed-by: Jia Liu pro...@gmail.com
static inline void wb_SR_F(void)
{
int label;
--
1.7.10.4
Regards,
Jia
.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/cputimer.c | 29 +++--
target-openrisc/cpu.h| 1 +
target-openrisc/sys_helper.c | 38
.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/interrupt.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/target-openrisc/interrupt.c b/target-openrisc
From: Sebastian Macke sebast...@macke.de
The test cases did not correctly test for the carry flag.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
tests/tcg/openrisc/test_addc.c | 8 +---
tests/tcg
From: Sebastian Macke sebast...@macke.de
Pages should be flagged executable only if the tlb executable flag is
set or the mmu is off.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/mmu.c | 4
From: Sebastian Macke sebast...@macke.de
The mtspr and mfspr routines didn't check for the correct memory boundaries.
This fixes a segmentation fault while booting Linux.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro
Hi Anthony,
Hi Blue,
This is my OpenRISC patch queue for 1.7, it have been well tested, please pull.
Thanks to Sebastian Macke, it made move optimization and fix some bugs.
The following changes since commit 394cfa39ba24dd838ace1308ae24961243947fb8:
Merge remote-tracking branch
for this special case.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 50 -
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git
From: Sebastian Macke sebast...@macke.de
The sr_f variable is only used for the l.bf and l.bnf instructions.
For clarity the code is also rewritten using a switch statement instead
of if chaining.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off
Hi Sebastian,
On Wed, Oct 30, 2013 at 5:22 AM, Sebastian Macke sebast...@macke.de wrote:
On 29/10/2013 2:15 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de
wrote:
Hi,
This is the second part of the patches to make the openrisc target faster
Hi Sebastian,
On Mon, Oct 28, 2013 at 9:56 AM, Sebastian Macke sebast...@macke.de wrote:
On 25/10/2013 5:21 PM, Jia Liu wrote:
On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke sebast...@macke.de
wrote:
On 22/10/2013 8:47 PM, Jia Liu wrote:
Hi Sebastian,
On Tue, Oct 22, 2013 at 8:12 AM
On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke sebast...@macke.de wrote:
On 22/10/2013 8:47 PM, Jia Liu wrote:
Hi Sebastian,
On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de
wrote:
This series is the first part to make the OpenRISC target more
reliable and faster
to
a significant speed improvement.
For v2 0/9 - 9/9
Acked-by: Jia Liu pro...@gmail.com
I'll add some comment into the code to explain why we separate flags from sr
and send a pull request if nobody raise a rejection.
Sebastian Macke (9):
target-openrisc: Speed up move instruction
Hi Peter,
On Thu, Oct 17, 2013 at 5:15 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 17 October 2013 04:17, Jia Liu pro...@gmail.com wrote:
On Fri, Oct 11, 2013 at 10:41 AM, Jia Liu pro...@gmail.com wrote:
I'm not sure about why qemu-system-or32 is not working on OS X, is it
a AREG0
Hi all,
On Fri, Oct 11, 2013 at 10:41 AM, Jia Liu pro...@gmail.com wrote:
Hi all,
I'm not sure about why qemu-system-or32 is not working on OS X, is it
a AREG0 problem? May you please give me some suggestion, I want to
test it on OS X, not Ubuntu any longer.
GCC on OS X is OK, it looks like
Hi Anthony,
Hi Peter,
On Thu, Oct 3, 2013 at 5:00 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 October 2013 17:41, Jia Liu pro...@gmail.com wrote:
Hi Anthony,
This is my OpenRISC patch queue. It originally come from Sebastian Macke,
split by me, and I used some comment come from
Hi all,
I'm not sure about why qemu-system-or32 is not working on OS X, is it
a AREG0 problem? May you please give me some suggestion, I want to
test it on OS X, not Ubuntu any longer.
Thank you.
Regards,
Jia
From: Sebastian Macke sebast...@macke.de
The result of (rw 0) is always zero and therefore a logic false.
The whole comparison will therefore never be executed, it is a obvious bug,
we should use !(rw 1) here.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro
Hi Anthony,
This is my OpenRISC patch queue. It originally come from Sebastian Macke,
split by me, and I used some comment come from Stefan Kristiansson.
Please pull.
This patch set correct two problems. The first one corrects one obvious
bug concerning the handling of page faults while reading
From: Sebastian Macke sebast...@macke.de
Where *software* leaves 0x - 0x2000 unmapped, the hardware should
still allow for this area to be mapped.
Signed-off-by: Sebastian Macke sebast...@macke.de
Signed-off-by: Stefan Kristiansson stefan.kristians...@saunalahti.fi
Reviewed-by: Jia Liu pro
Hi Peter,
On Thu, Oct 3, 2013 at 5:00 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 October 2013 17:41, Jia Liu pro...@gmail.com wrote:
Hi Anthony,
This is my OpenRISC patch queue. It originally come from Sebastian Macke,
split by me, and I used some comment come from Stefan
On Wed, Oct 2, 2013 at 2:15 PM, Stefan Kristiansson
stefan.kristians...@saunalahti.fi wrote:
On Wed, Oct 2, 2013 at 8:33 AM, Jia Liu pro...@gmail.com wrote:
Hi Sebastian,
On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke sebast...@macke.de
wrote:
Hi,
this patch corrects two problems
Hi Sebastian,
On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke sebast...@macke.de wrote:
Hi,
this patch corrects two problems for the OpenRISC Target in QEMU. The first
one corrects one obvious bug
concerning the handling of page faults while reading from a page.
@@ -102,7 +102,7 @@ int
(CPUState *cpu)
-{
-CPUXtensaState *env = XTENSA_CPU(cpu)-env;
-
-return env-pending_irq_level;
-}
-
#endif
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3
-static inline int cpu_mmu_index(CPUXtensaState *env)
-{
-return xtensa_get_cring(env);
-}
-
#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
target-openrisc: Tested-by: Jia Liu pro
@@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
}
cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
env = cpu-env;
-env-cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
(cpu_pc, dc-pc);
gen_exception(dc, EXCP_DEBUG);
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
)
raise_exception_err(env1, cpu-exception_index, env1-error_code);
#else
-cpu_loop_exit(env1);
+cpu_loop_exit(cpu);
#endif
}
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
fault */
-cpu_restore_state(env, pc);
+cpu_restore_state(cpu, pc);
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
);
+tlb_flush(CPU(cpu), 1);
}
}
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
);
if (xtensa_option_enabled(env-config,
XTENSA_OPTION_REGION_TRANSLATION)) {
entry-paddr = pte REGION_PAGE_MASK;
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
, page_size);
} else {
cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env-pc, ret, vaddr);
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Hi Peter,
On Fri, Aug 23, 2013 at 10:09 PM, Peter Maydell
peter.mayd...@linaro.org wrote:
On 21 August 2013 03:06, Jia Liu pro...@gmail.com wrote:
This is my OpenRISC patch queue for 1.7, it have been well tested, please
pull
Hi Peter,
On Tue, Aug 20, 2013 at 9:00 PM, Peter Maydell peter.mayd...@linaro.org wrote:
Ping for qemu-trivial now 1.7 is open.
Thank you, I'll send a PULL very soon.
thanks
-- PMM
On 5 August 2013 19:24, Peter Maydell peter.mayd...@linaro.org wrote:
clang warns that
xi.w...@gmail.com
Acked-by: Jia Liu pro...@gmail.com
---
hw/openrisc/pic_cpu.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
index ca0b7c1..3fcee02 100644
--- a/hw/openrisc/pic_cpu.c
+++ b/hw/openrisc/pic_cpu.c
@@ -26,7
to fetch changes up to 7717f248eebdcfe6de400404d0cf65dcb3633308:
hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler() (2013-08-21
09:31:42 +0800)
Jia Liu (3):
hw/openrisc: Avoid using uninitialised variable 'entry
In C99 signed shift (1 31) is undefined behavior, since the result
exceeds INT_MAX. Use 1U instead and move the shift after the check.
Signed-off-by: Xi Wang xi.w...@gmail.com
Acked-by: Jia Liu pro...@gmail.com
---
hw/openrisc/pic_cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion
/openrisc/openrisc_sim.c:91:19: note: uninitialized use occurs here
cpu-env.pc = entry;
^
Fix this by not attempting to change the CPU's starting PC unless
we actually loaded a kernel.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Jia Liu pro...@gmail.com
the masking of PICSR and PICMR:
((cpu-env.picsr (1 i)) (cpu-env.picmr (1 i)))
To correctly mask bits, we should use the bitwise AND rather than
the logical AND . Also, the loop is not necessary for masking.
Simply use (cpu-env.picsr cpu-env.picmr).
Cc: Jia Liu pro...@gmail.com
Cc
Hi Xi,
On Wed, Aug 14, 2013 at 1:55 PM, Xi Wang xi.w...@gmail.com wrote:
In C99 signed shift (1 31) is undefined behavior, since the result
exceeds INT_MAX. Use 1U instead and move the shift after the check.
Cc: Jia Liu pro...@gmail.com
Cc: Paolo Bonzini pbonz...@redhat.com
Signed-off
Hi Richard,
On Sat, Aug 10, 2013 at 3:19 AM, Richard Henderson r...@twiddle.net wrote:
We have one host platform (aarch64), and three target platforms
(openrisc, unicore32, xtensa) with no built-in disassembly support,
thanks largely to gplv3 silliness.
Thank you for doing this for or32.
(QEMUMachineInitArgs *args)
Thank you for using clang test it.
Reviewed-by: Jia Liu pro...@gmail.com
--
1.7.9.5
Regards,
Jia
);
occ-parent_realize(dev, errp);
}
target-openrisc Tested-by: Jia Liu pro...@gmail.com
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8215946..3c81798 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7861,6 +7861,8 @@ static void
Hi Xi,
On Tue, Jan 22, 2013 at 11:57 PM, Xi Wang xi.w...@gmail.com wrote:
A correct mask should be `x (1 i)', rather than `x (1 i)'.
Also, in C99 signed shift (1 31) is undefined behavior, since the
result exceeds INT_MAX; use 1U instead.
Signed-off-by: Xi Wang xi.w...@gmail.com
---
registered for AlphaCPU (fe31e7374299c0c6172ce618b29bf2fecbd881c7)
and OpenRISCCPU (da69721460e652072b6a3dd52b7693da21ffe237). Fix this.
Cc: Richard Henderson r...@twiddle.net
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
exec.c | 5 -
1 file changed, 4
vmstate_openrisc_cpu = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
-VMSTATE_CPU(),
VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
VMSTATE_END_OF_LIST()
}
Tested-by: Jia Liu pro...@gmail.com
in openrisc_cpu_class_by_name (2013-07-23
18:32:30 +0800)
Jia Liu (3):
hw/openrisc: Indent typo
hw/openrisc: Use stderr output instead of qemu_log
target-openrisc: Free typename in openrisc_cpu_class_by_name
hw
Indent typo.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Andreas Färber afaer...@suse.de
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Andreas Färber afaer...@suse.de
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2
, make any and or1200 works both OK.
Jia Liu (4):
hw/openrisc: Indent typo
hw/openrisc: Use stderr output instead of qemu_log
target-openrisc: Free typename
target-openrisc: Fix cpu_model by name
hw/openrisc/openrisc_sim.c | 6 +++---
target-openrisc/cpu.c | 17 +
2 files
Indent typo.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..250f5b5 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7
Fix cpu_model by name, make any and or1200 works both OK.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index e348df0..6637166 100644
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index
Hi Andreas,
On Mon, Jul 22, 2013 at 4:56 PM, Jia Liu pro...@gmail.com wrote:
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
Sorry I didn't know I need add Signed-off-by: Andreas Färber your@mail here.
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion
Hi Andreas and Peter,
On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 July 2013 09:56, Jia Liu pro...@gmail.com wrote:
Fix cpu_model by name, make any and or1200 works both OK.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 16
On Mon, Jul 22, 2013 at 5:41 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 July 2013 10:37, Jia Liu pro...@gmail.com wrote:
Hi Andreas,
On Mon, Jul 22, 2013 at 4:56 PM, Jia Liu pro...@gmail.com wrote:
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
Sorry I
On Mon, Jul 22, 2013 at 5:43 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 July 2013 10:42, Jia Liu pro...@gmail.com wrote:
Hi Andreas and Peter,
On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
This looks a bit odd. The commit message suggests it's
On Mon, Jul 22, 2013 at 5:43 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 July 2013 10:42, Jia Liu pro...@gmail.com wrote:
Hi Andreas and Peter,
On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
This looks a bit odd. The commit message suggests it's
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
Indent typo.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..250f5b5 100644
Hi Peter,
On Fri, Jul 19, 2013 at 5:27 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 July 2013 01:25, Jia Liu pro...@gmail.com wrote:
Hi Peter,
On Thu, Jul 18, 2013 at 6:18 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
Ping?
Thank you, it looks good to me, please push
Hi Peter,
On Thu, Jul 18, 2013 at 6:18 PM, Peter Maydell peter.mayd...@linaro.org wrote:
Ping?
Thank you, it looks good to me, please push it.
thanks
-- PMM
On 6 July 2013 21:44, Peter Maydell peter.mayd...@linaro.org wrote:
OpenRISC uses the asm-generic versions of target_stat and
Hi Andreas,
On Tue, Jul 16, 2013 at 10:19 PM, Andreas Färber afaer...@suse.de wrote:
Am 16.07.2013 04:00, schrieb Jia Liu:
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc
2 indent typo.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..f0dabb9 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc
Add a g_free into openrisc_cpu_class_by_name to free typename.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b
Here should be stderr output instead of qemu_log.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..26bff75 100644
--- a/hw/openrisc
Fix OpenRISC CPU and sim broad, in cpu.c we should free typename,
and in openrisc_sim.c we should use stderr output.
Jia Liu (2):
target-openrisc: free typename in cpu_class_by_name
hw/openrisc: Use stderr output instead of qemu_log
hw/openrisc/openrisc_sim.c | 2 +-
target-openrisc/cpu.c
Fix OpenRISC CPU and sim broad, we should free typename and check cpu models
by name in cpu.c, and we should use stderr output in openrisc_sim.c.
Jia Liu (4):
hw/openrisc: Indent typo
hw/openrisc: Use stderr output instead of qemu_log
target-openrisc: Free typename
target-openrisc: Fix
Indent typo.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..f0dabb9 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc
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