Re: [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0

On Mon, Sep 27, 2021 at 1:01 PM Vineet Gupta wrote: > So I obviously forgot to get the equivalent binutils branch, but the > only rvb branch on sifive fork feels dated > > > https://github.com/riscv-collab/riscv-binutils-gdb/tree/riscv-binutils-2.35-rvb That is the right branch to use with the

Re: [PATCH v5 0/4] target-riscv: support vector extension part 1

On Wed, Feb 26, 2020 at 2:36 PM Alistair Francis wrote: > On Wed, Feb 26, 2020 at 12:09 PM Jim Wilson wrote: > > If this rvv 0.7.1 implementation is considered a temporary solution, > > maybe we can just remove all of this work when the official rvv spec if > > avail

Re: [PATCH v5 4/4] target/riscv: add vector configure instruction

On 2/21/20 1:45 AM, LIU Zhiwei wrote: +/* Using x0 as the rs1 register specifier, encodes an infinite AVL */ +if (a->rs1 == 0) { +/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ +s1 = tcg_const_tl(RV_VLEN_MAX); This is wrong for the current draft of the

Re: [PATCH v5 3/4] target/riscv: support vector extension csr

On 2/21/20 1:45 AM, LIU Zhiwei wrote: +/* Vector Fixed-Point round model */ +#define FSR_VXRM_SHIFT 9 +#define FSR_VXRM(0x3 << FSR_VXRM_SHIFT) + +/* Vector Fixed-Point saturation flag */ +#define FSR_VXSAT_SHIFT 8 +#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) These

Re: [PATCH v5 0/4] target-riscv: support vector extension part 1

On 2/21/20 1:45 AM, LIU Zhiwei wrote: This is the first part of v5 patchset. The changelog of v5 is only coverd the part1. Features: * support specification riscv-v-spec-0.7.1. I'm still concerned about versioning issues. This implements an unofficial draft of the proposed RISC-V vector

Re: [PATCH v3 3/4] RISC-V: support vector extension csr

On 1/2/20 7:33 PM, LIU Zhiwei wrote: Until v0.7.1 specification, vector status is still not defined for mstatus. The v0.8 spec does define a VS bit in mstatus. @@ -107,11 +112,6 @@ static int pmp(CPURISCVState *env, int csrno) /* User Floating-Point CSRs */ static int

Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line

On 1/2/20 7:33 PM, LIU Zhiwei wrote: +if (cpu->cfg.vlen > RV_VLEN_MAX) { +error_setg(errp, + "Vector extension VLEN must <= %d", RV_VLEN_MAX); +return; There is no architectural maximum for VLEN. This is simply an

Re: [PATCH v2] target/riscv: Expose "priv" register for GDB

On Tue, Oct 8, 2019 at 2:00 AM Bin Meng wrote: > My gdb does not list "priv" register after applying this patch. I didn't try the patch, I didn't have time for that. I would expect priv to be in the "info registers" output if you are adding it to the cpu register set. Shrug. Anyways, defining

Re: [PATCH v2] target/riscv: Expose "priv" register for GDB

On 10/4/19 8:16 AM, Jonathan Behrens wrote: diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml index 0d07aaec85..d6d76aafd8 100644 --- a/gdb-xml/riscv-32bit-cpu.xml +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -44,4 +44,5 @@ + Adding this to the cpu register set

Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions

-bit. To allow RVF without RVD, changes to riscv_gdb_get_fpu() and riscv_gdb_set_fpu() were necessary. Reviewed-by: Jim Wilson Jim

Re: [Qemu-devel] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions

On 8/20/19 7:39 AM, Georg Kotheimer wrote: The size of the FPU registers depends solely on the floating point extensions supported by the target architecture. However, in the previous implementation the floating point register size was derived from whether the target architecture is 32-bit or

Re: [Qemu-devel] [PATCH v16 1/5] linux-user: Add support for translation of statx() syscall

On Fri, Jun 28, 2019 at 5:53 PM Aleksandar Markovic wrote: > This patch went trough several transformations in last few days, and I am a > little worried that we forgot the primary reasons/scenarios why want it in > the first place. In that light, may I ask you to recheck this latest version >

Re: [Qemu-devel] [PATCH v10 3/3] linux-user: Add support for statx() syscall

On Tue, Jun 18, 2019 at 4:13 PM Aleksandar Markovic wrote: > I am waiting on him to send a new version of the series. Meanwhile you can > send strace patch to the list, and I can even incude it in my series after > and together with Aleksandar's patch, if you don't object. I submitted it the

Re: [Qemu-devel] [PATCH] linux-user: Add strace support for statx.

On Tue, Jun 18, 2019 at 5:09 PM wrote: > === OUTPUT BEGIN === > ERROR: storage class should be at the beginning of the declaration > #25: FILE: linux-user/strace.c:979: > +UNUSED static struct flags statx_flags[] = { It is complaining about UNUSED, which is a macro that expands to attribute

[Qemu-devel] [PATCH] linux-user: Add strace support for statx.

toolchain. Signed-off-by: Jim Wilson --- linux-user/strace.c| 86 ++ linux-user/strace.list | 3 ++ 2 files changed, 89 insertions(+) diff --git a/linux-user/strace.c b/linux-user/strace.c index 6f72a74..c80e93b 100644 --- a/linux-user/strace.c

[Qemu-devel] [PATCH] RISC-V: Update syscall list for 32-bit support.

32-bit RISC-V uses _llseek instead of lseek as syscall number 62. Update syscall list from open-embedded build, primarily because 32-bit RISC-V requires statx support. Tested with cross gcc testsuite runs for rv32 and rv64, with the pending statx patch also applied. Signed-off-by: Jim Wilson

Re: [Qemu-devel] [PATCH v10 3/3] linux-user: Add support for statx() syscall

On 6/7/19 3:35 AM, Aleksandar Markovic wrote: Implement support for translation of system call statx(). I also need these patches for 32-bit RISC-V linux user mode support. glibc ld.so calls statx if fstatat is not supported. Apparently new linux architecture ports aren't allowed to define

[Qemu-devel] [PATCH v4 4/5] RISC-V: Add debug support for accessing CSRs.

Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function to set it. Disable mode checks when debugger field true. Signed-off-by: Jim Wilson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 + target/riscv/csr.c | 34 ++ 2 files

[Qemu-devel] [PATCH v4 2/5] RISC-V: Add 64-bit gdb xml files.

Signed-off-by: Jim Wilson Reviewed-by: Alistair Francis --- configure | 1 + gdb-xml/riscv-64bit-cpu.xml | 43 gdb-xml/riscv-64bit-csr.xml | 250 gdb-xml/riscv-64bit-fpu.xml | 52 + 4 files changed, 346

[Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files.

The gdb CSR xml file has registers in documentation order, not numerical order, so we need a table to map the register numbers. This also adds fairly standard gdb hooks to access xml specified registers. Signed-off-by: Jim Wilson --- target/riscv/cpu.c | 9 +- target/riscv/cpu.h

[Qemu-devel] [PATCH v4 3/5] RISC-V: Fixes to CSR_* register macros.

This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Signed-off-by: Jim Wilson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 35 +-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/target

[Qemu-devel] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files.

Signed-off-by: Jim Wilson Reviewed-by: Alistair Francis --- configure | 1 + gdb-xml/riscv-32bit-cpu.xml | 43 gdb-xml/riscv-32bit-csr.xml | 250 gdb-xml/riscv-32bit-fpu.xml | 46 4 files changed, 340

[Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support.

This is the 4th version of the patch set. Updated as per the review from Alistair, it has the riscv_csrrw_debug function added, and Reviewed-By lines added. Otherwise it is the same as the 3rd version. Jim

Re: [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.

On Fri, Feb 8, 2019 at 10:17 AM Alistair Francis wrote: > Can we just write a wrapper function then that sets and unsets the variable? > Something like this: > > riscv_csrrw_debug(...) { > #if !defined(CONFIG_USER_ONLY) > env->debugger = true; > #endif > result =

Re: [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.

On Wed, Feb 6, 2019 at 4:04 PM Alistair Francis wrote: > Would it not be easier to add an extra argument to the functions > intstead of setting and unsetting this? > > That's what you had in the earlier version of this set. The csr support was rewritten, and is now a table of functions. If I

[Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.

The gdb CSR xml file has registers in documentation order, not numerical order, so we need a table to map the register numbers. This also adds fairly standard gdb hooks to access xml specified registers. Signed-off-by: Jim Wilson --- target/riscv/cpu.c | 9 +- target/riscv/cpu.h

[Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs.

Adds a debugger field to CPURISCVState. Disable mode checks in riscv_csrrw when true. Signed-off-by: Jim Wilson --- target/riscv/cpu.h | 3 +++ target/riscv/csr.c | 16 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

[Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros.

This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Signed-off-by: Jim Wilson --- target/riscv/cpu_bits.h | 35 +-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv

[Qemu-devel] [PATCH 2/5 v3] RISC-V: Add 64-bit gdb xml files.

Signed-off-by: Jim Wilson --- configure | 1 + gdb-xml/riscv-64bit-cpu.xml | 43 gdb-xml/riscv-64bit-csr.xml | 250 gdb-xml/riscv-64bit-fpu.xml | 52 + 4 files changed, 346 insertions(+) create mode 100644 gdb

[Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files.

Signed-off-by: Jim Wilson --- configure | 1 + gdb-xml/riscv-32bit-cpu.xml | 43 gdb-xml/riscv-32bit-csr.xml | 250 gdb-xml/riscv-32bit-fpu.xml | 46 4 files changed, 340 insertions(+) create mode 100644 gdb

[Qemu-devel] [PATCH 0/5 v3] RISC-V: Add gdb xml files and gdbstub support.

This is the 3rd version of the patch set, updated as per the review from Richard and Alistair, and updated for current top of tree. Parts 1 and 2 are the same. Part 3 is smaller because some of it was moved to part 5. Part 5 is bigger because it received part of part 3. Parts 4 and 5 have

Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

On Tue, Jan 22, 2019 at 1:45 PM Alistair Francis wrote: > I think it makes more sense to just define the variable in the > gdbstubs.c file then. Can you move it to patch 5? Yes, that is no problem. That makes patch 3 a lot smaller and patch 5 a lot bigger, but it is the same code as before,

Re: [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.

On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis wrote: > You can get env and then check for floating point support: > > CPURISCVState *env = >env; > if (env->misa_mask & RVF) { > ... I needed this which wasn't hard to figure out. RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = >env;

Re: [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.

On Sat, Dec 29, 2018 at 2:20 PM Richard Henderson wrote: > On 12/29/18 9:07 AM, Jim Wilson wrote: > Don't the csr's vary between priv-1.9.1 and priv-1.10? There are a few csr's that disappear in 1.10, but there is no known hardware that implements them. There are a few csr's new in 1.10,

Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson wrote: > On 12/29/18 9:09 AM, Jim Wilson wrote: > > +int csr_register_map[] = { > > static const? If I add static const here, then I get a build error if this patch is applied to the tree but the following patch #5 that us

[Qemu-devel] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support.

This is the second version of the patch set. I haven't gotten any bug reports for the patches in the several weeks that they have been available, and no review yet, so the only significant difference from the first version is that I ran them through checkpatch to fix style issues, and I sent them

[Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.

Signed-off-by: Jim Wilson --- configure | 1 + gdb-xml/riscv-32bit-cpu.xml | 43 gdb-xml/riscv-32bit-csr.xml | 250 gdb-xml/riscv-32bit-fpu.xml | 46 4 files changed, 340 insertions(+) create mode 100644 gdb

[Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.

Adds a debugger parameter to csr_read_helper and csr_write_helper. When this is true, we disable illegal instruction checks. Signed-off-by: Jim Wilson --- linux-user/riscv/signal.c | 5 ++- target/riscv/cpu.h| 7 +++- target/riscv/cpu_helper.c | 4 +- target/riscv/gdbstub.c| 4

[Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files.

Signed-off-by: Jim Wilson --- configure | 1 + gdb-xml/riscv-64bit-cpu.xml | 43 gdb-xml/riscv-64bit-csr.xml | 250 gdb-xml/riscv-64bit-fpu.xml | 52 + 4 files changed, 346 insertions(+) create mode 100644 gdb

[Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.

Signed-off-by: Jim Wilson --- target/riscv/cpu.c | 9 ++- target/riscv/gdbstub.c | 73 -- 2 files changed, 73 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a025a0a..b248e3e 100644 --- a/target

[Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

The gdb CSR xml file has registers in documentation order, not numerical order, so we need a table to map the register numbers. This also adds some missing CSR_* register macros. Signed-off-by: Jim Wilson --- target/riscv/cpu_bits.h | 35 ++- target/riscv/csr-map.h | 248

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson <richard.hender...@linaro.org> wrote: > On 01/24/2018 10:58 AM, Jim Wilson wrote: >> Although, looking at this again, I see another statement in a >> different place that says: >> >> Except when otherwise stated,

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

On Tue, Jan 23, 2018 at 4:15 PM, Richard Henderson wrote: > Ok. Now it depends on what result you care about for madd specifically. > > If, like x86 and Power, fmsub returns the (silenced) original input NaN, you > want the float_muladd_* flags. > > If, like ARM,

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

On Tue, Jan 23, 2018 at 3:35 PM, Michael Clark wrote: > We want minimum number (minnum). It's been added to the draft spec and will > be in riscv-spec-v2.3.pdf In the preface of the draft, it says • Defined the signed-zero behavior of FMIN.fmt and FMAX.fmt, and changed their