Hello Philippe!
On 16/08/2021 10:01, Philippe Mathieu-Daudé wrote:
On 8/16/21 2:36 PM, Jose R. Ziviani wrote:
If users try to add an isa-vga device that was already registered,
still in command line, qemu will crash:
$ qemu-system-mips64el -M pica61 -device isa-vga
RAMBlock "vga.vram" already
Hello Thomas and Gerd,
Thank you for reviewing it. Sending a v2 soon.
Thank you very much!
On 16/08/2021 02:05, Gerd Hoffmann wrote:
Hi,
+if (qemu_ram_block_by_name("vga.vram")) {
+error_report("vga.vram is already registered, ignoring this device");
+return;
+}
I
ualization type: para
L1d cache: 32K
L1i cache: 32K
NUMA node0 CPU(s): 0-15
Note: it's also possible to simulate SMT in TCG single threaded mode.
Signed-off-by: Jose Ricardo Ziviani
---
hw/ppc/spapr.c | 5 -
target/ppc/exc
-system-ppc64: Error -22 while loading VM state
$
Signed-off-by: Jose Ricardo Ziviani
---
migration/savevm.c | 4 +++-
vl.c | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/migration/savevm.c b/migration/savevm.c
index 13e51f0e34..9692577318 100644
--- a/migr
From: Jose Ricardo Ziviani
We need to set cs->halted to 1 before calling ppc_set_compat. The reason
is that ppc_set_compat kicks up the new thread created to manage the
hotplugged KVM virtual CPU and the code drives directly to KVM_RUN
ioctl. When cs->halted is 1, the code:
int kvm_cp
4096 \
-smp 4,maxcpus=8,sockets=1,cores=2,threads=4 \
-display none -nographic \
-drive file=disk1.qcow2,format=qcow2
...
(qemu) device_add host-spapr-cpu-core,core-id=4
[no interaction is possible after it, only SIGKILL to take the terminal
back]
Signed-off-by: Jose Ricardo Ziviani
---
rd
Signed-off-by: Jose Ricardo Ziviani
---
accel/kvm/kvm-all.c | 4
1 file changed, 4 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 071f4f57c0..f290f487a5 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -812,10 +812,6 @@ static void kvm_mem_ioe
This reverts commit 4fe6d78b2e241f41208dfb07605aace4becfc747.
As reported
http://lists.nongnu.org/archive/html/qemu-devel/2018-01/msg05457.html
The referred commit is causing regression issues in virtio.
Signed-off-by: Jose Ricardo Ziviani
Reported-by: Anton Blanchard
---
accel/kvm/kvm-all.c
Jose Ricardo Ziviani
---
hw/ppc/spapr.c | 10 ++
target/ppc/kvm.c | 5 +
target/ppc/kvm_ppc.h | 6 ++
3 files changed, 21 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d1acfe8858..aed4d25fc4 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2261,12 +22
ports it displays an
error message and quits:
qemu-system-ppc64: KVM does not support 8 threads/core.
Available VSMT modes: 4 2 1.
Jose Ricardo Ziviani (2):
ppc: Change Power9 compat table to support at most 8 threads/core
ppc: spapr: Check if thread argument is supported by host KVM
h
tplug.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/compat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index ad8f93c064..d1770cdc6f 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -73,7 +73,7 @@ static const Compa
=0xc00d30ac thread_id=80200
CPU #4: nip=0xc00d30ac thread_id=80201
CPU #5: nip=0xc00d30ac thread_id=80202
CPU #6: nip=0xc00d30ac thread_id=80203
CPU #7: nip=0xc00d30ac thread_id=80204
This patch is based on ppc-for-2.12
Jose Ricardo Ziviani (1
ower9 guests to have 8 threads/core
if desired.
Reported-by: Satheesh Rajendran
Signed-off-by: Jose Ricardo Ziviani
---
hw/ppc/spapr.c | 14 +-
hw/ppc/trace-events | 1 +
target/ppc/kvm.c | 5 +
target/ppc/kvm_ppc.h | 6 ++
4 files changed, 25 insertions(
#x27;
This patch improves this error by adding a hint instead of just that
KeyError log:
$ scripts/simpletrace.py trace-events trace-68508
'qemu_mutex_locked' event is logged but is not declared in the trace
events file, try using trace-events-all instead.
Signed-off-by: Jose Ricardo Ziv
and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contribut
--pattern "ADD" ppc64.risu test.bin
Signed-off-by: Jose Ricardo Ziviani
---
risugen | 6 +-
risugen_ppc64.pm | 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 6aad626..8b20425 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +26
same: only some fixes in configure and risugen.
Also, it adds a better random initialization of VSX registers.
Jose Ricardo Ziviani (4):
risugen_ppc64: Load random 128-bit data to vector registers
configure: Add initial support to PPC64 (big endian)
risugen,risugen_ppc64.pm: Add support ppc64
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 42 +++---
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 341478c..1a3cd59 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -99,6
Uses the same ppc64 source file for both BE/LE archs since they are
essentially the same thing.
Signed-off-by: Jose Ricardo Ziviani
---
configure | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/configure b/configure
index 055e6d6..dd64d8b 100755
--- a/configure
<7d2a482a> 7924cfe3
41820040 79260022
[17582052553.370599] ---[ end trace 9470442ed18ae727 ]---
As soon as we identify and fix the issue that's causing such problem
I'll re-send the referred patch to re-enable TCE.
Signed-off-by: Jose Ricardo Ziviani
CC: Bharata B Rao
---
hw/ppc/sp
se it:
trace-event qemu_mutex_lock on|off
trace-event qemu_mutex_unlock on|off
or
trace-event qemu_mutex* on|off
Signed-off-by: Jose Ricardo Ziviani
---
v2:
- removed unecessary (void*) cast
- renamed parameter name to lock instead of qemu_global_mutex
util/qemu-thread-posix.c | 5 +
util/
it:
trace-event qemu_mutex_lock on|off
trace-event qemu_mutex_unlock on|off
or
trace-event qemu_mutex* on|off
Signed-off-by: Jose Ricardo Ziviani
---
util/qemu-thread-posix.c | 5 +
util/trace-events| 4
2 files changed, 9 insertions(+)
diff --git a/util/qemu-thread-posix.c b/util/q
(0001:03:00.0:region1+0xc0, 0xbfd0008, 8)
qemu_mutex_unlock unlocked mutex 0x10905ad8
Signed-off-by: Jose Ricardo Ziviani
---
hw/vfio/common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 145f2f4..43c8e98 100644
--- a/hw/vfio/common.
memory.c:access_with_adjusted_size() in order to be under
the same lock. Today, it's done in exec.c:address_space_write_continue()
which was able to handle only 4 bytes due to a zero'ed
valid.max_access_size (see exec.c:memory_access_size()).
Signed-off-by: Jose Ricardo Ziviani
---
hw/vfio/common.c | 4
1 file
This patchset has two patches:
[1] 8-byte writes to non-mapped MMIO are broken into pairs of 4-byte writes,
this patch makes such pairs atomic.
[2] Enable 8-byte accesses in vfio_region_write and vfio_region_read.
Patches based on master.
Jose Ricardo Ziviani (2):
vfio: Set
v2:
- applied code review
This patchset include initial support to PPC64 (Big-Endian), that is pretty
much the same: only some fixes in configure and risugen.
Also, it adds a better random initialization of VSX registers.
Jose Ricardo Ziviani (3):
risugen_ppc64: Load random 128-bit data to
--pattern "ADD" ppc64.risu test.bin
Signed-off-by: Jose Ricardo Ziviani
---
risugen | 6 +-
risugen_ppc64.pm | 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 6aad626..086173c 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +26
This commit set Makefile to point to ppc64le source for both archs
(ppc64 and ppc64le) because they do the exact same thing. The
difference is in risugen and how the binary is build.
Signed-off-by: Jose Ricardo Ziviani
---
configure | 9 -
1 file changed, 4 insertions(+), 5 deletions
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 40 +---
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 341478c..45f7220 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -99,6 +99,29
Signed-off-by: Jose Ricardo Ziviani
---
risu_reginfo_ppc64le.c | 8
1 file changed, 8 deletions(-)
diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
index e6bc0e0..a76f296 100644
--- a/risu_reginfo_ppc64le.c
+++ b/risu_reginfo_ppc64le.c
@@ -86,14 +86,6 @@ int reginfo_is_eq
This patchset include initial support to PPC64 (Big-Endian), that is pretty
much the same: only some fixes in configure and risugen.
Also, it adds a better random initialization of VSX registers.
And does some cleanup.
Jose Ricardo Ziviani (5):
risugen_ppc64: Load random 128-bit data to VSX
Because we don't support custom fpsrc value yet it's better to remove
that code.
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 4
1 file changed, 4 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 46ab7b1..4f7c709 100644
--- a/risugen_ppc6
--pattern "ADD" ppc64.risu test.bin
Signed-off-by: Jose Ricardo Ziviani
---
risugen | 6 +-
risugen_ppc64.pm | 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 6aad626..086173c 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +26
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 40 +---
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index cb75300..28b6792 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -99,6 +99,29
This commit set Makefile to point to ppc64le source for both archs
(ppc64 and ppc64le) because they do the exact same thing. The
difference is in risugen and how the binary is build.
Signed-off-by: Jose Ricardo Ziviani
---
configure | 9 -
1 file changed, 4 insertions(+), 5 deletions
Signed-off-by: Jose Ricardo Ziviani
---
test_ppc64le.s | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/test_ppc64le.s b/test_ppc64le.s
index af23ea3..4af770c 100644
--- a/test_ppc64le.s
+++ b/test_ppc64le.s
@@ -12,15 +12,15
Signed-off-by: Jose Ricardo Ziviani
---
risu_reginfo_ppc64le.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
index 7a54eab..e6bc0e0 100644
--- a/risu_reginfo_ppc64le.c
+++ b/risu_reginfo_ppc64le.c
@@ -105,9 +105,9
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 40f3d4f..561c17b 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -75,6 +75,13 @@ sub write_add_ri
Register R1 is defined as the stack frame pointer and R13 is the thread
local storage by ABI. So, in order to let the program flows, they are
better to keep unchanged.
Signed-off-by: Jose Ricardo Ziviani
---
test_ppc64le.s | 2 --
1 file changed, 2 deletions(-)
diff --git a/test_ppc64le.s b
This patchset contains some fixes and improvements for ppc64le.
Jose Ricardo Ziviani (7):
risu_ppc64le: improve xsrqpi[x] and xsrqpxp instructions
risu_ppc64le: fix 32-bit mov immediate
risu_ppc64le: implement sign extend for small neg constants
risu_ppc64le: implement FP random data for
Two instructions are necessary but the high value should be written
first, shifted 16 bit left, and then or'ed the lower value. This commit
fixes the problem.
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --
This commit replaces the simple FP data written for tests for a
randomically generated one. This functionality stores the same data in
FP register and VSX[VRB+32] registers.
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 31 +++
1 file changed, 31
New constraint added to the referred instructions in order to avoid
generation of reserved (not used today) rounding modes for floating
point operations.
Signed-off-by: Jose Ricardo Ziviani
---
ppc64.risu | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/ppc64.risu b
xssqrtqp: VSX Scalar Square Root Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/fpu_helper.c | 38 +
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/fpu_helper.c | 56 +
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc
implemented when round-to-odd is ready.
Jose Ricardo Ziviani (4):
ppc: implement xsrqpi[x] instruction
ppc: implement xsrqpxp instruction
ppc: implement xssqrtqp instruction
ppc: implement xssubqp instruction
target/ppc/fpu_helper.c | 188
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer
[with Inexact].
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/fpu_helper.c | 60 +
target/ppc/helper.h | 1 +
target/ppc/internal.h | 1 +
target/ppc
xssubqp: VSX Scalar Subtract Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/fpu_helper.c | 34 ++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4
4;
This patch set regs to a valid location as well as other sigcontext
fields.
Signed-off-by: Jose Ricardo Ziviani
---
linux-user/signal.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 5064de0..8209539 100644
--- a/linux-user/signal.c
++
When running FP operations, FPSCR flag must be compared to make sure
that any exception will behave consistently.
Signed-off-by: Jose Ricardo Ziviani
---
risu_reginfo_ppc64le.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
index 4dc509c
Qemu linux-user doesn't fill uc_mcontext completely like full emul. does.
For instance, uc->uc_mcontext.regs->nip is an invalid so this
commit replaces it by uc->uc_mcontext.gp_regs[PT_NIP]
Signed-off-by: Jose Ricardo Ziviani
---
risu_ppc64le.c | 2 +-
risu_reginfo_
This patchset contains a fix necessary to run Risu under linux-user, that is
due to the fact that linux-user doesn't fully implement ucontext struct. It
also contains an small improvement to validate FPSRC flag for floating-point
operations.
Jose Ricardo Ziviani (2):
risu_ppc64: Fix Ri
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 51 +
target/ppc/translate/vmx-impl.inc.c | 4
WER9 ISA3.0, left/right shifts for
unsigned quadwords and a small improvement to check whether a bcd value is
valid or not.
bcdtrunc.: Decimal signed trucate
bcdutrunc.: Decimal unsigned truncate
Jose Ricardo Ziviani (2):
ppc: Implement bcdtrunc. instruction
ppc: Implement bcdutrunc. ins
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 37
This commit fixes a warning in the code "(i * 2) ? .. : ..", which
should be better as "i ? .. : ..", and improves the BCD_DIG_BYTE
macro by placing parentheses around its argument to avoid possible
expansion issues like: BCD_DIG_BYTE(i + j).
Signed-off-by: Jose Ricardo Zivian
This commit fixes a warning in the code "(i * 2) ? .. : ..", which
should be better as "(i) ? .. : ..", and improves the BCD_DIG_BYTE
macro by placing parentheses around its argument to avoid possible
expansion issues like: BCD_DIG_BYTE(i + j).
Signed-off-by: Jose Ricardo Zivi
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 41
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 40
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c |
igh, 250, &overflow);
equivalent: n << 122
urshift(&low, &high, -2);
equivalent: n << 126
Signed-off-by: Jose Ricardo Ziviani
---
include/qemu/host-utils.h | 27 +
tests/Makefile.include| 5 +-
tests/test-shift128.c | 139 +
It is not possible to implement functions in host-utils.c for
architectures with quadwords because the guard is implemented in the
Makefile. This patch move the guard out of the Makefile to the
implementation file.
Signed-off-by: Jose Ricardo Ziviani
---
util/Makefile.objs | 2 +-
util/host
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 37
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 51 +
target/ppc/translate/vmx-impl.inc.c | 4
value is
valid or not.
bcds.: Decimal signed shift
bcdus.: Decimal unsigned shift
bcdsr.: Decimal shift and round
bcdtrunc.: Decimal signed trucate
bcdutrunc.: Decimal unsigned truncate
Jose Ricardo Ziviani (7):
host-utils: Move 128-bit guard macro to .c file
host-utils: Implement unsigned
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 51 +
target-ppc/translate/vmx-impl.inc.c | 4
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 37
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 41
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c |
This commit implements functions to right and left shifts and the
unittest for them. Such functions is needed due to instructions
that requires them.
Today, there is already a right shift implementation in int128.h
but it's designed for signed numbers.
Signed-off-by: Jose Ricardo Zi
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 40
dwords and a small improvement to check whether a bcd value is
valid or not.
bcds.: Decimal signed shift
bcdus.: Decimal unsigned shift
bcdsr.: Decimal shift and round
bcdtrunc.: Decimal signed trucate
bcdutrunc.: Decimal unsigned truncate
Jose Ricardo Ziviani (6):
target-ppc: Implement unsigne
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 40
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 54 +
target-ppc/translate/vmx-impl.inc.c | 4
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c |
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 43
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 38
This commit implements functions to right and left shifts and the
unittest for them. Such functions is needed due to instructions
that requires them.
Today, there is already a right shift implementation in int128.h
but it's designed for signed numbers.
Signed-off-by: Jose Ricardo Zi
is
valid or not.
bcds.: Decimal signed shift
bcdus.: Decimal unsigned shift
bcdsr.: Decimal shift and round
bcdtrunc.: Decimal signed trucate
bcdutrunc.: Decimal unsigned truncate
Jose Ricardo Ziviani (6):
target-ppc: Implement unsigned quadword left/right shift and unit
tests
target-ppc:
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 39 +
target-ppc/translate/vmx-impl.inc.c | 4
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c |
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 43
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 43
A function to check if all digits of a given BCD number is valid is
here presented because more instructions will need to reuse the
same code.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/int_helper.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff
This commit implements functions to right and left shifts and the
unittest for them. Such functions is needed due to instructions
that requires them.
Today, there is already a right shift implementation in int128.h
but it's for signed numbers.
Signed-off-by: Jose Ricardo Ziviani
---
in
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 38
small improvement to check whether a bcd value is
valid or not.
bcds.: Decimal signed shift
bcdus.: Decimal unsigned shift
bcdsr.: Decimal shift and round
bcdtrunc.: Decimal signed trucate
bcdtrunc.: Decimal unsigned truncate
Jose Ricardo Ziviani (7):
target-ppc: Implement bcd_is_valid function
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 43
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 39 +
target-ppc/translate/vmx-impl.inc.c | 4
This commit implements functions to right and left shifts and the
unittest for them. Such functions is needed due to instructions
that requires them.
Today, there is already a right shift implementation in int128.h
but it's for signed numbers.
Signed-off-by: Jose Ricardo Ziviani
---
in
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c |
bcdtrunc.: Decimal unsigned truncate
Jose Ricardo Ziviani (7):
target-ppc: Implement bcd_is_valid function
target-ppc: Implement unsigned quadword left/right shift and unit
tests
target-ppc: Implement bcds. instruction
target-ppc: Implement bcdus. instruction
target-ppc: Implement
A function to check if all digits of a given BCD number is valid is
here presented because more instructions will need to reuse the
same code.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/int_helper.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 38
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 43
bcdsetsgn.: Decimal set sign. This instruction copies the register
value to the result register but adjust the signal according to
the preferred sign value.
Signed-off-by: Jose Ricardo Ziviani
Reviewed-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c
bcdctsq.: Decimal convert to signed quadword. It is possible to
convert packed decimal values to signed quadwords.
Signed-off-by: Jose Ricardo Ziviani
Reviewed-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 40
bcdcpsgn.: Decimal copy sign. Given two registers vra and vrb, it
copies the vra value with vrb sign to the result register vrt.
Signed-off-by: Jose Ricardo Ziviani
Reviewed-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 23
bcdcfsq.: Decimal convert from signed quadword. It is not possible
to convert values less than -10^31-1 or greater than 10^31-1 to be
represented in packed decimal format.
Signed-off-by: Jose Ricardo Ziviani
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c
sign
Jose Ricardo Ziviani (4):
target-ppc: Implement bcdcfsq. instruction
target-ppc: Implement bcdctsq. instruction
target-ppc: Implement bcdcpsgn. instruction
target-ppc: Implement bcdsetsgn. instruction
target-ppc/helper.h | 4 ++
target-ppc/int_helper.c
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