On Thu, 2 Aug 2018 15:56:47 -0600
Sandra Loosemore wrote:
> On 05/18/2018 03:35 PM, Sandra Loosemore wrote:
> > On 05/18/2018 02:19 PM, Julian Brown wrote:
> >> On Fri, 18 May 2018 21:52:04 +0200
> >> Marek Vasut wrote:
> >>
> >>> On 05/18/
This patch (by Sandra Loosemore, mildly rebased) adds support for
semihosting for Nios II bare-metal emulation.
Signed-off-by: Julian Brown
Signed-off-by: Sandra Loosemore
---
qemu-options.hx| 8 +-
target/nios2/Makefile.objs | 2 +-
target/nios2/cpu.h | 4 +-
target
unwinding to work when binaries are linked to start at the
beginning of the address space.
The generic_nommu.c parts are by Andrew Jenner, based on code by Marek
Vasut.
Originally by Marek Vasut and Andrew Jenner.
Signed-off-by: Julian Brown
Signed-off-by: Andrew Jenner
Signed-off-by: Marek Vasut
#x27;s new libgloss bits as mentioned in:
http://lists.nongnu.org/archive/html/qemu-devel/2018-08/msg00358.html
Thanks,
Julian
Julian Brown (2):
Add generic Nios II board.
Add Nios II semihosting support.
hw/nios2/Makefile.objs | 2 +-
hw/nios2/boot.c| 5 +-
On Fri, 18 May 2018 21:52:04 +0200
Marek Vasut wrote:
> On 05/18/2018 09:23 PM, Julian Brown wrote:
> > This patch (by Sandra Loosemore, mildly rebased) adds support for
> > semihosting for Nios II bare-metal emulation.
> >
> > Signed-off-by: Julian Brown
> >
On Fri, 18 May 2018 21:50:55 +0200
Marek Vasut wrote:
> On 05/18/2018 09:23 PM, Julian Brown wrote:
> > This patch adds support for a generic MMU-less Nios II board that
> > can be used e.g. for bare-metal compiler testing. Nios II booting
> > is also tweaked so that bare
This patch (by Sandra Loosemore, mildly rebased) adds support for
semihosting for Nios II bare-metal emulation.
Signed-off-by: Julian Brown
Signed-off-by: Sandra Loosemore
---
qemu-options.hx| 8 +-
target/nios2/Makefile.objs | 2 +-
target/nios2/cpu.h | 4 +-
target
This is a third attempt at sending the patch series:
http://lists.gnu.org/archive/html/qemu-devel/2018-05/msg04259.html
Turns out the git format-patch "--inline" option didn't do what I thought
it did. Apologies for the noise!
Thanks,
Julian
Julian Brown (2):
Add generi
unwinding to work when binaries are linked to start at the
beginning of the address space.
The generic_nommu.c parts are by Andrew Jenner, based on code by Marek
Vasut.
Originally by Marek Vasut and Andrew Jenner.
Signed-off-by: Julian Brown
Signed-off-by: Andrew Jenner
Signed-off-by: Marek Vasut
unwinding to work when binaries are linked to start at the
beginning of the address space.
The generic_nommu.c parts are by Andrew Jenner, based on code by Marek
Vasut.
Originally by Marek Vasut and Andrew Jenner.
Signed-off-by: Julian Brown
Signed-off-by: Andrew Jenner
Signed-off-by: Marek Vasut
This patch (by Sandra Loosemore, mildly rebased) adds support for
semihosting for Nios II bare-metal emulation.
Signed-off-by: Julian Brown
Signed-off-by: Sandra Loosemore
---
qemu-options.hx| 8 +-
target/nios2/Makefile.objs | 2 +-
target/nios2/cpu.h | 4 +-
target
This is a second attempt at sending this patch series:
http://lists.gnu.org/archive/html/qemu-devel/2018-05/msg04259.html
with some git format-patch/send-email hiccups ironed out
(hopefully). The patch contents are unchanged.
OK, or any comments?
Thanks,
Julian
Julian Brown (2):
Add
unwinding to work when binaries are linked to start at the
beginning of the address space.
The generic_nommu.c parts are by Andrew Jenner, based on code by Marek
Vasut.
Signed-off-by: Julian Brown
---
hw/nios2/Makefile.objs | 2 +-
hw/nios2/boot.c | 5 +-
hw/nios2/generic_nommu.c | 128
internal builds successfully with these patches.
OK, or any comments?
Thanks,
Julian
Julian Brown (2):
Add generic Nios II board.
Add Nios II semihosting support.
hw/nios2/Makefile.objs | 2 +-
hw/nios2/boot.c| 5 +-
hw/nios2/generic_nommu.c | 128 ++
This patch (by Sandra Loosemore, mildly rebased) adds support for
semihosting for Nios II bare-metal emulation.
Signed-off-by: Julian Brown
---
qemu-options.hx| 8 +-
target/nios2/Makefile.objs | 2 +-
target/nios2/cpu.h | 4 +-
target/nios2/helper.c | 11
for BE32 system mode.
Signed-off-by: Julian Brown
---
include/exec/softmmu-arm-semi.h | 131
target/arm/arm-semi.c | 4 +-
target/arm/cpu.c| 24
target/arm/cpu.h| 6 ++
4 files changed, 163 insertions
.
This version of the patch augments and tidies up comments a little.
Signed-off-by: Julian Brown
---
exec.c | 1 +
include/qom/cpu.h | 3 +++
qom/cpu.c | 6 ++
target/arm/cpu.c | 3 +++
target/arm/internals.h | 5 +
target/arm/op_helper.c | 22
egratorcp board init do so too.
Signed-off-by: Julian Brown
---
hw/arm/integratorcp.c | 19 +--
target/arm/cpu.c | 14 ++
target/arm/cpu.h | 7 +++
3 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integra
-swap the data to/from GDB in those cases.
Signed-off-by: Julian Brown
---
target/arm/gdbstub.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 04c1208..1e9fe68 100644
--- a/target/arm/gdbstub.c
+++ b
dency problems for my taste).
Signed-off-by: Julian Brown
---
gdbstub.c | 11 ---
include/exec/cpu-all.h | 22 ++
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 64f2696..cb77e15 100644
--- a/gdbstub.c
+++ b/gdbs
tches". It's less complicated to just read the correct
two bytes though.)
Signed-off-by: Julian Brown
---
disas.c | 1 +
include/disas/bfd.h | 7 +++
target/arm/arm_ldst.h | 10 +-
target/arm/cpu.c | 23 +++
4 files changed, 40 insertions
round of
reviews, apologies in advance if I've missed anything.
Thanks,
Julian
Julian Brown (7):
Add cfgend parameter for ARM CPU selection.
Honour reset_sctlr EE/B bits during reset.
Move target_memory_rw_debug function.
ARM big-endian semihosting support.
ARM big-endian system-mo
ot; for the same purpose:
this version avoids that, and also avoids fiddling with info->endianness
setting.)
Signed-off-by: Julian Brown
---
hw/arm/boot.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index ff621e4..c059bd2 100644
On Thu, 19 Jan 2017 15:12:49 +
Peter Maydell wrote:
> I'm actually looking at a patch at the moment that attempts
> to fix this by adding a cpu_generic_init_unrealized(),
> which does everything that cpu_generic_init() does except
> the final "set the realized prop to true" step, so that you
On Wed, 11 Jan 2017 12:35:52 +
Julian Brown wrote:
> I'm a little confused, I think -- these changes seemed to be necessary
> to allow the parsing of the command-line syntax you suggested earlier
> (-mcpu=foo,cfgend=bar):
> [...]
> Can the existing properties be set like
On Thu, 5 Jan 2017 17:17:13 +
Peter Maydell wrote:
> > +qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
> > + &error_abort);
> > +
> > +qdev_prop_set_globals(DEVICE(obj));
> > +
> > +if (object_property_get_bool(obj, "cfgend", NULL)) {
>
erform denormal arithmetic properly: in our case, selecting
a Cortex-A8 CPU when using QEMU as an instruction-set simulator for
bare-metal GCC testing caused tests using denormal arithmetic to
fail. Problems might be masked (or not occur) when using a full OS kernel
with suitable trap handlers (I&
.
Signed-off-by: Julian Brown
---
exec.c | 1 +
include/qom/cpu.h | 1 +
qom/cpu.c | 6 ++
target-arm/cpu.c | 3 +++
target-arm/internals.h | 5 +
target-arm/op_helper.c | 22 ++
6 files changed, 38 insertions(+)
diff --git a
disassembly.
Signed-off-by: Julian Brown
---
disas.c | 1 +
include/disas/bfd.h | 7 +++
target-arm/arm_ldst.h | 10 +-
target-arm/cpu.c | 32
4 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/disas.c b/disas.c
index
-swap the data to/from GDB in those cases.
Signed-off-by: Julian Brown
---
target-arm/gdbstub.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
index 04c1208..1e9fe68 100644
--- a/target-arm/gdbstub.c
+++ b
-off-by: Julian Brown
---
include/exec/softmmu-arm-semi.h | 148
target-arm/arm-semi.c | 4 +-
target-arm/cpu.c| 24 +++
target-arm/cpu.h| 6 ++
4 files changed, 180 insertions(+), 2 deletions(-)
create
cfgend=yes \
-kernel /dev/null
(gdb) load
(gdb) [...]
In this scenario, the usual method of probing the kernel binary for the
correct endianness to use will not work.
Signed-off-by: Julian Brown
---
hw/arm/boot.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
di
This is the second iteration of a series of patches to implement
semihosting/gdbstub support for big-endian ARM system mode. The previous
series started here:
http://lists.nongnu.org/archive/html/qemu-devel/2016-11/msg00646.html
Thanks,
Julian
Julian Brown (6):
Add cfgend parameter for ARM
PUs implementing the ARMv7+ architecture will enable the SCTLR_EE bit,
and for previous versions it will enable the SCTLR_B bit.
Signed-off-by: Julian Brown
---
target-arm/cpu.c | 28 +---
target-arm/cpu.h | 7 +++
2 files changed, 32 insertions(+), 3 deletions(-)
dif
The patch works for me! Thank you!
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https://bugs.launchpad.net/bugs/1647683
Title:
Bad interaction between tb flushing & gdb stub
Status in QEMU:
New
Bug description:
I have been
On Tue, 6 Dec 2016 15:44:07 +
Peter Maydell wrote:
> On 6 December 2016 at 15:11, Julian Brown
> wrote:
> > On Thu, 3 Nov 2016 22:23:09 +
> > Peter Maydell wrote:
> >
> >> Strong 'no' for the approach of having different CPU
> >&g
I'm testing the patch now, thank you! I'll report back on how it goes.
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https://bugs.launchpad.net/bugs/1647683
Title:
Bad interaction between tb flushing & gdb stub
Status in QEMU:
On Fri, 4 Nov 2016 14:04:24 +
Julian Brown wrote:
> On Fri, 4 Nov 2016 13:30:12 +
> Peter Maydell wrote:
>
> > On 3 November 2016 at 17:30, Julian Brown
> > wrote:
> > > Thumb-1 code has some issues in BE32 mode (as currently
> > > implemen
ory ownership with the GLIB
functions -- I don't have a good handle on that, really, but I think
it's OK.)
Thanks,
Julian>From d76129fb9ab60df696af6bc4911041f95b3a560b Mon Sep 17 00:00:00 2001
From: Julian Brown
Date: Tue, 1 Nov 2016 08:35:48 -0700
Subject: [PATCH 1/4] ARM BE8/BE32 semi
On Fri, 4 Nov 2016 09:55:17 +0100
Paolo Bonzini wrote:
> On 04/11/2016 00:20, Julian Brown wrote:
> > On Thu, 3 Nov 2016 23:14:05 +
> > Peter Maydell wrote:
> >
> >> On 3 November 2016 at 17:30, Julian Brown
> >> wrote:
> >>> In BE32
On Fri, 4 Nov 2016 10:00:19 +0100
Paolo Bonzini wrote:
> On 03/11/2016 18:30, Julian Brown wrote:
> > +#ifdef CONFIG_USER_ONLY
> > size = be32_to_cpu(size);
> > +#else
> > +/* If we're running in BE32 system mode, we don't need to do
> > an
(FAOD, the crashes happen without Valgrind too, and the above backtrace
may be a red herring.)
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1647683
Title:
Bad interaction between tb flushing & gdb
Public bug reported:
I have been working on a series of patches for ARM big-endian system
mode support, using QEMU as a bare-metal simulator for the GDB test
suite. At some point I realised that these tests were not running
reliably on the QEMU master branch, even without my patches applied.
(I.e.
On Fri, 4 Nov 2016 13:30:12 +
Peter Maydell wrote:
> On 3 November 2016 at 17:30, Julian Brown
> wrote:
> > Thumb-1 code has some issues in BE32 mode (as currently
> > implemented). In short, since bytes are swapped within words at
> > load time for BE32 executable
On Fri, 4 Nov 2016 09:48:06 +0100
Paolo Bonzini wrote:
> On 04/11/2016 00:34, Julian Brown wrote:
> >
> > So (IIRC!) the gdbstub needs to interpret some of these read/write
> > values on the host, i.e. in host byte ordering. "Traditionally", the
> > ldl_p a
On Thu, 3 Nov 2016 22:23:09 +
Peter Maydell wrote:
> On 3 November 2016 at 17:30, Julian Brown
> wrote:
> > This patch improves support for semihosting and debugging with the
> > in-built gdbstub for ARM system-mode emulation in big-endian mode
> > (either BE8 or
On Thu, 3 Nov 2016 23:14:05 +
Peter Maydell wrote:
> On 3 November 2016 at 17:30, Julian Brown
> wrote:
> > In BE32 mode, sub-word size watchpoints can fail to trigger because
> > the address of the access is adjusted in the opcode helpers before
> > being comp
This appears to be a typo in arm_cpu_do_interrupt_aarch32 (OR'ing with ~CPSR_E
instead of CPSR_E).
Signed-off-by: Julian Brown
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 25b15dc..b5b65ca 1
In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers. This patch reversed the address
adjustment before performing the comparison.
Signed-off-by: Julian Brown
disassembly.
Signed-off-by: Julian Brown
---
disas/arm.c | 46 +++---
include/disas/bfd.h | 1 +
target-arm/arm_ldst.h | 10 +-
target-arm/cpu.c | 4
4 files changed, 49 insertions(+), 12 deletions(-)
diff --git a/disas/arm.c b
This patch fixes the arm_semi_flen_cb callback so that it doesn't return
a byte-swapped size in BE32 system mode.
Signed-off-by: Julian Brown
---
target-arm/arm-semi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index a9
hould do.
Thank you,
Julian
Julian Brown (5):
ARM BE8/BE32 semihosting and gdbstub support.
Fix Thumb-1 BE32 execution and disassembly.
Fix arm_semi_flen_cb for BE32 system mode.
ARM BE32 watchpoint fix.
Fix typo in arm_cpu_do_interrupt_aarch32.
disas/arm.c | 46 +
o the
CPU on some hardware board to select endianness, which is a completely
legitimate thing to have, even if the implementation as-is is not really
ideal from a software-engineering standpoint. It suffices for our current
use-case though.
Signed-off-by: Julian Brown
---
hw/arm/boot.c
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