[PATCH v8 15/23] target/riscv: Split out the vill from vtype

We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c| 3 +-- target/riscv/csr.c | 13 - target/riscv/machine.c

[PATCH v8 13/23] target/riscv: Calculate address according to XLEN

Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++-- target

[PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN

When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- .../riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvi.c.inc | 5 ++-- target/riscv

[PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base]

Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 32 1 file changed, 8 insertions

[PATCH v8 23/23] target/riscv: Relax UXL field for debugging

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/csr.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 523d07a95e..e5f9d4ef93 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -584,7

[PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 4 +--- target/riscv/translate.c| 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans

[PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN

When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +-

[PATCH v8 11/23] target/riscv: Create current pm fields in env

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 4 target/riscv/cpu_helper.c | 43 +++ target/riscv/csr.c| 19 + target

[PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 19 +++ target/riscv/pmp.c | 12 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a9e7ac903b

[PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN

Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 12 target/riscv/op_helper.c| 3 ++- 2 files changed, 10 insertions(+), 5

[PATCH v8 09/23] target/riscv: Relax debug check for pm write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9be2820d2b..c00a82022e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c

[PATCH v8 07/23] target/riscv: Extend pc for runtime pc write

In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc register according to current xlen for these cases. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target

[PATCH v8 02/23] target/riscv: Don't save pc when exception return

As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7

[PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN

The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b

[PATCH v8 05/23] target/riscv: Create xl field in env

load. So that we can only recompute xlen in this places and cache it into CPURISCVState. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 31 +++ target/riscv/cpu_helper.c | 34

[PATCH v8 00/23] Support UXL filed in xstatus

sequence v2: Split out vill from vtype Remove context switch when xlen changes at exception Use XL instead of OL in many places Use pointer masking and XLEN for vector address Define an common fuction to calculate address for ld LIU Zhiwei (23): target/riscv: Adjust pmpcfg access with mxl

Re: [PATCH v7 21/22] target/riscv: Enable uxl field write

RT MHPM Count  : 0 Boot HART MIDELEG : 0x0666 Boot HART MEDELEG : 0x00f0b509 QEMU: Terminated Thanks, Zhiwei On 2022/1/20 上午11:29, Alistair Francis wrote: On Thu, Jan 20, 2022 at 12:12 PM LIU Zhiwei wrote: On 2022/1/20 上午8:35, Alistair Francis wrote: O

Re: [PATCH v7 21/22] target/riscv: Enable uxl field write

On 2022/1/20 上午8:35, Alistair Francis wrote: On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff

Re: [PATCH v7 21/22] target/riscv: Enable uxl field write

On 2022/1/20 上午8:35, Alistair Francis wrote: On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff

[PATCH v7 22/22] target/riscv: Relax UXL field for debugging

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/csr.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 90f78eca65..c6b2407a06 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -584,7

[PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN

When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +-

[PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE

Signed-off-by: LIU Zhiwei Acked-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe58ccaeae..55635d68d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -111,7

[PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base

Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 ++- target

[PATCH v7 18/22] target/riscv: Fix check range for first fault only

Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target

[PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 + target/riscv/vector_helper.c | 7 +-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6c740b92c1

[PATCH v7 09/22] target/riscv: Relax debug check for pm write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9be2820d2b..c00a82022e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c

[PATCH v7 13/22] target/riscv: Calculate address according to XLEN

Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++-- target

[PATCH v7 15/22] target/riscv: Split out the vill from vtype

We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c| 3 +-- target/riscv/csr.c | 13 - target/riscv/machine.c

[PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN

The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b

[PATCH v7 11/22] target/riscv: Create current pm fields in env

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 4 target/riscv/cpu_helper.c | 43 +++ target/riscv/csr.c| 19 + target

[PATCH v7 21/22] target/riscv: Enable uxl field write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b11d92b51b..90f78eca65 100644 --- a/target/riscv

[PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]

Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 32 1 file changed, 8 insertions

[PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN

When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- .../riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvi.c.inc | 5 ++-- target/riscv

[PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN

Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 12 target/riscv/op_helper.c| 3 ++- 2 files changed, 10 insertions(+), 5

[PATCH v7 19/22] target/riscv: Adjust vector address with mask

The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions

[PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 ++--- target/riscv/gdbstub.c | 71 +++--- 2 files changed, 55 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.c b/target

[PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 4 +--- target/riscv/translate.c| 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans

[PATCH v7 07/22] target/riscv: Extend pc for runtime pc write

In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc register according to current xlen for these cases. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target

[PATCH v7 05/22] target/riscv: Create xl field in env

load. So that we can only recompute xlen in this places and cache it into CPURISCVState. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 31 +++ target/riscv/cpu_helper.c | 34

[PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 19 +++ target/riscv/pmp.c | 12 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a9e7ac903b

[PATCH v7 02/22] target/riscv: Don't save pc when exception return

As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7

[PATCH v7 00/22] Support UXL filed in xstatus

Use XL instead of OL in many places Use pointer masking and XLEN for vector address Define an common fuction to calculate address for ld LIU Zhiwei (22): target/riscv: Adjust pmpcfg access with mxl target/riscv: Don't save pc when exception return target/riscv: Sign extend link reg

Re: [PATCH v6 05/22] target/riscv: Create xl field in env

On 2022/1/19 上午11:24, Alistair Francis wrote: On Thu, Jan 13, 2022 at 9:50 PM LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei I'm not clear on why this is better? Current xlen has been used in helper functions and many other places.  The computation of current xlen  is not so trivial, so

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf Signed-off-by: Guo Ren Tested-by: Bin Meng Reviewed-by: Liu Zhiwei Reviewed-by: Bin Meng Reviewed-by: Alistair Francis ---   target/riscv/cpu_bits.h   | 7 +++   target/riscv/cpu_helper.c | 2 +-   2 files

[PATCH v6 22/22] target/riscv: Relax UXL field for debugging

Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d944ee9caf..1037c6b15d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -580,7 +580,7 @@ static RISCVException

[PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN

When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion

[PATCH v6 18/22] target/riscv: Fix check range for first fault only

Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target

[PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 + target/riscv/vector_helper.c | 7 +-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index abf217e34f

[PATCH v6 21/22] target/riscv: Enable uxl field write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8e67ff7c54..d944ee9caf 100644 --- a/target/riscv

[PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base

Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 ++- target

[PATCH v6 15/22] target/riscv: Split out the vill from vtype

We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c| 3 +-- target/riscv/csr.c | 13 - target/riscv/machine.c

[PATCH v6 19/22] target/riscv: Adjust vector address with mask

The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions

[PATCH v6 13/22] target/riscv: Calculate address according to XLEN

Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++-- target

[PATCH v6 11/22] target/riscv: Create current pm fields in env

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 4 target/riscv/cpu_helper.c | 43 +++ target/riscv/csr.c| 19 + target

[PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]

Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 32 1 file changed, 8 insertions

[PATCH v6 09/22] target/riscv: Relax debug check for pm write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b282a642f5..3f3afbed21 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c

[PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 ++--- target/riscv/gdbstub.c | 71 +++--- 2 files changed, 55 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.c b/target

[PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE

Signed-off-by: LIU Zhiwei Acked-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 645a1b3f6c..85eb5c63cf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -110,7

[PATCH v6 05/22] target/riscv: Create xl field in env

Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 31 +++ target/riscv/cpu_helper.c | 34 ++ target/riscv/csr.c| 2 ++ target/riscv/machine.c| 10 ++ 5 files changed, 46

[PATCH v6 07/22] target/riscv: Extend pc for runtime pc write

In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc register according to current xlen for these cases. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target

[PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN

Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 12 target/riscv/op_helper.c| 3 ++- 2 files changed, 10 insertions(+), 5

[PATCH v6 04/22] target/riscv: Sign extend pc for different XLEN

When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- .../riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvi.c.inc | 5 ++-- target/riscv

[PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr

Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvi.c.inc | 4 +--- target/riscv/translate.c| 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 3a0ae28fef

[PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN

The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b

[PATCH v6 02/22] target/riscv: Don't save pc when exception return

As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7

[PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/csr.c | 19 +++ target/riscv/pmp.c | 12 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index adb3d4381d..e7578f3e0f 100644

[PATCH v6 00/22] Support UXL filed in xstatus

for vector address Define an common fuction to calculate address for ld LIU Zhiwei (22): target/riscv: Adjust pmpcfg access with mxl target/riscv: Don't save pc when exception return target/riscv: Sign extend link reg for jal and jalr target/riscv: Sign extend pc for different XLEN

Re: [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb

On 2021/11/23 下午5:09, LIU Zhiwei wrote: Only the pmp index that be checked by pmp_hart_has_privs can be used by pmp_get_tlb_size to avoid an error pmp index. Before modification, we may use an error pmp index. For example, we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs

[PATCH v4 1/1] target/riscv: Fix PMP propagation for tlb

as it is legal in pmp_get_tlb_size. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 16 ++- target/riscv/pmp.c| 58 +++ target/riscv/pmp.h| 6 ++-- 3 files changed, 34 insertions(+), 46 deletions(-) diff --git a/target/riscv

Re: [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb

On 2021/12/17 上午8:37, Alistair Francis wrote: On Wed, Dec 8, 2021 at 1:23 PM Alistair Francis wrote: On Tue, Nov 23, 2021 at 7:09 PM LIU Zhiwei wrote: Only the pmp index that be checked by pmp_hart_has_privs can be used by pmp_get_tlb_size to avoid an error pmp index. Before modification

[PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN

When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.c.inc | 44 ++---

[PATCH v5 19/22] target/riscv: Fix check range for first fault only

Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target

[PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1e56405243..2cee98f152 100644 --- a/target/riscv/cpu.h +++ b/target

[PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 + target/riscv/vector_helper.c | 7 +-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2cee98f152

[PATCH v5 22/22] target/riscv: Enable uxl field write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 8 +--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f77

[PATCH v5 14/22] target/riscv: Split out the vill from vtype

We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c| 3 +-- target/riscv/csr.c | 13 - target/riscv/machine.c

[PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base

Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 ++- target

[PATCH v5 20/22] target/riscv: Adjust vector address with mask

The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/riscv

[PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base]

Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 32 1 file changed, 8 insertions

[PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE

Signed-off-by: LIU Zhiwei Acked-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef1d87af38..347428ffdc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -106,7

[PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index

[PATCH v5 08/22] target/riscv: Relax debug check for pm write

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4ee897be2..bfafd3bd96 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c

[PATCH v5 04/22] target/riscv: Create xl field in env

Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 ++- target/riscv/csr.c| 2 ++ target/riscv/machine.c| 5 +++-- 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target

[PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN

Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/op_helper.c| 3 ++- 2 files changed, 4 insertions(+), 3 deletions

[PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN

The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH v5 12/22] target/riscv: Calculate address according to XLEN

Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++-- target

[PATCH v5 10/22] target/riscv: Create current pm fields in env

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 4 target/riscv/cpu_helper.c | 43 +++ target/riscv/csr.c| 19 + target/riscv/machine.c| 10

[PATCH v5 00/22] Support UXL filed in xstatus

fuction to calculate address for lds LIU Zhiwei (22): target/riscv: Adjust pmpcfg access with mxl target/riscv: Don't save pc when exception return target/riscv: Sign extend pc for different XLEN target/riscv: Create xl field in env target/riscv: Ignore the pc bits above XLEN target

[PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN

When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv

[PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++ target/riscv/gdbstub.c | 71 +++--- 2 files changed, 55 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl

Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 18 ++ target/riscv/pmp.c | 12 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..ce20c3a970 100644 --- a/target/riscv/csr.c +++ b/target/riscv

[PATCH v5 02/22] target/riscv: Don't save pc when exception return

As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7

[PATCH v5 06/22] target/riscv: Extend pc for runtime pc write

In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc register according to current xlen for these cases. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target

Re: [PATCH v2 0/5] Check PMP rules num before propagation

As I have found another similar error in PMP, and we can fix it at the same time. I have sent a patch named "target/riscv: Fix PMP propagation for tlb". This patch set should be dropped. Thanks, Zhiwei Drop this patch set. On 2021/11/22 下午7:02, LIU Zhiwei wrote: In this patch se

[PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb

as it is legal in pmp_get_tlb_size. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 16 ++- target/riscv/pmp.c| 56 +-- target/riscv/pmp.h| 6 ++--- 3 files changed, 31 insertions(+), 47 deletions(-) diff --git a/target/riscv

[PATCH v2 3/5] target/riscv: Discard return value for pmp_is_range_in_tlb

Signed-off-by: LIU Zhiwei --- target/riscv/pmp.c | 11 ++- target/riscv/pmp.h | 2 +- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index ca38087574..4850a9cc5d 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -620,16

[PATCH v2 5/5] target/riscv: Modify return and parameter type for pmp_adjust_tlb_size

Signed-off-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 3 ++- target/riscv/pmp.c| 13 +++-- target/riscv/pmp.h| 4 ++-- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index cf8109197d..45e29e6c01

[PATCH v2 2/5] target/riscv: Give a more generic size for tlb

As the caller has given a tlb size parameter, we should use it to keep pace with it. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 5 + target/riscv/pmp.c| 7 --- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv

[PATCH v2 1/5] target/riscv: Check PMP rules num before propagation

When an address is in [0-4K) and no pmp rule configured, the tlb_size will be set to 1. This is caused by pmp_get_tlb_size return a value 1. if (pmp_sa >= tlb_sa && pmp_ea <= tlb_ea) { return pmp_ea - pmp_sa + 1; } Here pmp_sa == 0 and pmp_ea == 0. Signed-off-by: LIU Zhiwe

[PATCH v2 4/5] target/riscv: Rename pmp_is_range_in_tlb

Signed-off-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 2 +- target/riscv/pmp.c| 2 +- target/riscv/pmp.h| 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3f53744897..cf8109197d 100644

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