Re: [PATCH v6 00/14] tcg/riscv: Add support for vector

On 2024/10/21 09:42, Alistair Francis wrote: On Thu, Oct 17, 2024 at 5:33 AM Richard Henderson wrote: Introduce support for the RISC-V vector extension in the TCG backend. v5: https://lore.kernel.org/qemu-devel/20241007025700.47259-1-zhiwei_...@linux.alibaba.com/ Changes for v6: - Fix p

Re: [PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU

On 2024/10/11 11:55, Alistair Francis wrote: On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei wrote: From: TANG Tiancheng We have implemented UXL32 on QEMU already. It enables us to run RV32 applications on RV64 Linux on QEMU. Similarly, RISCV specification doesn't limit the SXLEN to be the

Re: [PATCH v6 09/14] tcg/riscv: Accept constant first argument to sub_vec

); +return C_O1_I2(v, vK, v); Reviewed-by: LIU Zhiwei Zhiwei case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); case INDEX_op_cmpsel_vec:

Re: [PATCH v6 02/14] disas/riscv: Fix vsetivli disassembly

riscv.c +++ b/disas/riscv.c @@ -4808,7 +4808,7 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) break; case rv_codec_vsetivli: dec->rd = operand_rd(inst); -dec->imm = operand_vimm(inst); +dec->imm = extract32(inst, 15, 5); Reviewed-by: LIU Zhiwei Zhiwei dec->vzimm = operand_vzimm10(inst); break; case rv_codec_zcb_lb:

Re: [PATCH v6 01/14] tcg: Reset data_gen_ptr correctly

#ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_INIT(&s->ldst_labels); Reviewed-by: LIU Zhiwei Zhiwei

Re: [PATCH v3 1/8] target/riscv: Add Ssdbltrp CSRs handling

On 2024/10/17 17:12, Clément Léger wrote: On 17/10/2024 10:35, Clément Léger wrote: On 16/10/2024 11:40, LIU Zhiwei wrote: On 2024/10/14 19:22, Clément Léger wrote: Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on

Re: Host riscv disas is broken

On 2024/10/17 11:52, Richard Henderson wrote: On 10/16/24 19:57, LIU Zhiwei wrote: Hi Richard, On 2024/10/17 02:38, Richard Henderson wrote: 2595: if (dec->cfg->ext_zcmop) { 2690:    if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2716:   

Re: Host riscv disas is broken

Hi Richard, On 2024/10/17 02:38, Richard Henderson wrote: 2595: if (dec->cfg->ext_zcmop) { 2690:    if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2716:    if (!dec->cfg->ext_zcmt) { 2726:    if (!dec->cfg->ext_zcmp) { 4028:   

Re: [PATCH v3 1/8] target/riscv: Add Ssdbltrp CSRs handling

On 2024/10/14 19:22, Clément Léger wrote: Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu

Re: [PATCH v5 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

On 2024/10/8 00:24, Richard Henderson wrote: On 10/6/24 19:56, LIU Zhiwei wrote: +static void probe_frac_lmul(void) +{ +    unsigned long vlmax[3]; + +    for (int i = MO_8; i <= MO_64; ++i) { +    switch (i) { +    case MO_8: +    asm volatile( +    "vs

[PATCH v1 6/7] target/riscv: Reset SXL and UXL according to sxl32

From: TANG Tiancheng When boot a 32-bit system, sxl and uxl should be set to 1 by OpenSBI. However, OpenSBI does not support this feature. We temporarily force QEMU reset SXL and UXL to MXL_RV32 when sxl32 is enabled. Signed-off-by: TANG Tiancheng --- target/riscv/cpu.c | 13 +++-- 1

[PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU

From: TANG Tiancheng Enable with "-cpu rv64,sxl32=on". When sxl32 is enabled, RV64 can boot 32-bit Linux with 64-bit Opensbi while requiring to make minor modifications to the Linux kernel source code. How to patch linux: https://git Signed-off-by: TANG Tiancheng --- target/riscv/cpu.c | 1 +

[PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32

From: TANG Tiancheng Allow reading 32-bit only registers like timeh and stimecmph when booting a 32-bit Linux kernel on RV64 when sxl32 is true. Signed-off-by: TANG Tiancheng --- target/riscv/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/tar

[PATCH v1 4/7] hw/riscv: Align kernel to 4MB when sxl32 is on.

From: TANG Tiancheng RISC-V always requires 4MB alignment for RV32. Signed-off-by: TANG Tiancheng --- hw/riscv/boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 1a2c1ff9e0..7ce0d8f08f 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv

[PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW

From: TANG Tiancheng Satp and PTE are always SXLEN-bit. when SXLEN is 32, read PTE as 4 bytes, and treat satp as SATP32. Signed-off-by: TANG Tiancheng --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/

[PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly.

QEMU RV64. Signed-off-by: TANG Tiancheng Fixes: c7b9517188 (RISC-V: Implement modular CSR helper interface) Reviewed-by: Liu Zhiwei --- target/riscv/cpu_cfg.h | 4 target/riscv/csr.c | 25 +++-- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/target/

[PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU

From: TANG Tiancheng We have implemented UXL32 on QEMU already. It enables us to run RV32 applications on RV64 Linux on QEMU. Similarly, RISCV specification doesn't limit the SXLEN to be the same with MXLEN. In this patch set, we will go forward to implement SXL32 on RV64 CPU. SXL is one filed i

[PATCH v1 1/7] target/riscv: Fix sstatus read and write

From: TANG Tiancheng Sstatus is SXLEN bits in length and always has the layout determined by the SXL configuration, regardless of the current XLEN. Signed-off-by: TANG Tiancheng Fixes: b550f89457 (target/riscv: Compute mstatus.sd on demand) Fixes: f310df58bd (target/riscv: Enable uxl field writ

[PATCH v5 12/12] tcg/riscv: Enable native vector support for TCG host

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index e6d66cd1b9..d27007f2e6 100644

[PATCH v5 11/12] tcg/riscv: Implement vector roti/v/x ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 6 +++--- 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv

[PATCH v5 10/12] tcg/riscv: Implement vector shi/s/v ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 76 ++ tcg/riscv/tcg-target.h | 6 +-- 3 files changed, 80 insertions

[PATCH v5 09/12] tcg/riscv: Implement vector min/max ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 + tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg

[PATCH v5 08/12] tcg/riscv: Implement vector sat/mul ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv

[PATCH v5 07/12] tcg/riscv: Implement vector neg ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 7 +++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg

[PATCH v5 06/12] tcg/riscv: Implement vector cmp/cmpsel ops

x27;s cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Expand cmp with cmpsel. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target-con-str.h

[PATCH v5 05/12] tcg/riscv: Add support for basic vector opcodes

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 ++ tcg/riscv/tcg-target.c.inc | 52 ++ tcg/riscv/tcg-target.h | 2 +- 3 files changed, 55 insertions

[PATCH v5 04/12] tcg/riscv: Implement vector mov/dup{m/i}

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 73 -- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg

[PATCH v5 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

multi-threaded TCG. Signed-off-by: TANG Tiancheng Signed-off-by: Weiwei Li Reviewed-by: Liu Zhiwei --- include/tcg/tcg.h | 7 + tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target.c.inc | 334 - 3 files changed, 338 insertions(+), 5

[PATCH v5 02/12] tcg/riscv: Add basic support for vector

d-off-by: Huang Shiyuan Co-authored-by: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 126 - tcg/riscv/tcg-target.h

[PATCH v5 00/12] tcg/riscv: Add support for vector

From: TANG Tiancheng This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets. v5: 1. Improve the signature of co-authors 2. Add probe for fractional LMUL setting. 3. Fix bug of INDEX_op_rotlv_vec. 4. Modify the author's alias swung0x48 to hi

[PATCH v5 01/12] util: Add RISC-V vector extension probe in cpuinfo

nsion. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- host/include/riscv/host/cpuinfo.h | 2 ++ util/cpuinfo-riscv.c | 24 ++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpui

Re: [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

On 2024/9/22 12:46, Richard Henderson wrote: On 9/11/24 15:26, LIU Zhiwei wrote: @@ -2129,6 +2389,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)     static void tcg_out_tb_start(TCGContext *s)   { +    s->riscv_cur_type = TCG_TYPE_COUNT;   /* nothing to do */   } I recen

Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector

nt out. Thanks, Zhiwei Best Regards, Swung0x48 (aka. Huang Shiyuan) Get Outlook for Android <https://aka.ms/AAb9ysg> -------- *From:* Richard Henderson *Sent:* Wednesday, September 18, 2024 10:27:16 PM *To:* LIU Zhiwei

Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector

t Regards, Swung0x48 (aka. Huang Shiyuan) Get Outlook for Android <https://aka.ms/AAb9ysg> -------- *From:* Richard Henderson *Sent:* Wednesday, September 18, 2024 10:27:16 PM *To:* LIU Zhiwei ; qemu-devel@nongnu.org *Cc:* qemu-ri...@no

[PATCH v7 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32

From: TANG Tiancheng Ensure pmp_size is correctly determined using mxl for RV32 in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b

[PATCH v7 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64

From: TANG Tiancheng Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. This is required as MMU address translations run in S-mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 17 - 1

[PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU

make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \ TuxRunBaselineTest:test_riscv64_rv32 Signed-off-by: LIU Zhiwei Suggested-by: Daniel Henrique Barboza --- tests/avocado/tuxrun_baselines.py | 16 1 file changed, 16 insertions(+) diff --git a/tests/avocado

[PATCH v7 7/8] target/riscv: Add max32 CPU for RV64 QEMU

n RV32 CPU. Signed-off-by: LIU Zhiwei Suggested-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 12 +++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4464c0fd7a..62115375cd 10

[PATCH v7 6/8] target/riscv: Enable RV32 CPU support in RV64 QEMU

From: TANG Tiancheng Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- configs/targets/riscv64-softmmu.mak | 2 +- target/riscv/cpu.c | 16

[PATCH v7 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU

From: TANG Tiancheng Ensure mcause high bit is correctly set by using 32-bit width for RV32 mode and 64-bit width for RV64 mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 ++-- 1 file changed, 6 insertions(+), 2

[PATCH v7 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU

From: TANG Tiancheng Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an RV64 QEMU. Signed-off-by: TANG Tiancheng Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64") Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.h |

[PATCH v7 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI

From: TANG Tiancheng RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead of target_ulong. In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI. We create a fw_dynmaic_info32 struct for this purpose. Signed-off-by: TANG Tiancheng Reviewed-by: Liu

[PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU

v2: Remove the line that was inadvertently left in PATCH v1 4/6. Add an avocado test. v1: https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html LIU Zhiwei (2): target/riscv: Add max32 CPU for RV64 QEMU tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU TANG Tian

Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector

On 2024/9/18 18:11, Richard Henderson wrote: On 9/18/24 07:17, LIU Zhiwei wrote: On 2024/9/12 2:41, Richard Henderson wrote: On 9/11/24 06:26, LIU Zhiwei wrote: From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length

Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector

On 2024/9/12 2:41, Richard Henderson wrote: On 9/11/24 06:26, LIU Zhiwei wrote: From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each

Re: [PATCH v4 01/12] util: Add RISC-V vector extension probe in cpuinfo

On 2024/9/12 2:34, Richard Henderson wrote: On 9/11/24 06:26, LIU Zhiwei wrote: While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. Language is incorrect here.  The compiler has nothing to do with it. Perhaps "If the installed kernel he

[PATCH v4 04/12] tcg/riscv: Implement vector mov/dup{m/i}

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 73 -- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 47f4e35237

[PATCH v4 06/12] tcg/riscv: Implement vector cmp/cmpsel ops

x27;s cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Expand cmp with cmpsel. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target-con-str.h | 2 + tcg/riscv/tcg-target.

[PATCH v4 02/12] tcg/riscv: Add basic support for vector

ff-by: TANG Tiancheng Co-authored-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 126 - tcg/riscv/tcg-target.h | 78 +++- tcg/riscv/tcg-target.opc.h | 12 4

[PATCH v4 00/12] tcg/riscv: Add support for vector

From: TANG Tiancheng This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets. v4: 1. Move the implementation of roti/s/v_vec from tcg_expand_vec_op to tcg_out_vec_op, not just shi_vec. 2. Put shi and shs/v in the same patch. 3. Put load/store a

[PATCH v4 01/12] util: Add RISC-V vector extension probe in cpuinfo

division into subtraction. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- host/include/riscv/host/cpuinfo.h | 2 ++ util/cpuinfo-riscv.c | 24 ++-- 2

[PATCH v4 10/12] tcg/riscv: Implement vector shi/s/v ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 76 ++ tcg/riscv/tcg-target.h | 6 +-- 3 files changed, 80 insertions(+), 3 deletions(-) diff --git

[PATCH v4 11/12] tcg/riscv: Implement vector roti/v/x ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 35 +++ tcg/riscv/tcg-target.h | 6 +++--- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv

[PATCH v4 12/12] tcg/riscv: Enable native vector support for TCG host

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index e6d66cd1b9..d27007f2e6 100644

[PATCH v4 08/12] tcg/riscv: Implement vector sat/mul ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv

[PATCH v4 09/12] tcg/riscv: Implement vector min/max ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 + tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg

[PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

multi-threaded TCG. Signed-off-by: TANG Tiancheng Signed-off-by: Weiwei Li Reviewed-by: Liu Zhiwei --- include/tcg/tcg.h | 7 + tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target.c.inc | 269 - 3 files changed, 274 insertions(+), 4

[PATCH v4 07/12] tcg/riscv: Implement vector neg ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 7 +++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg

[PATCH v4 05/12] tcg/riscv: Add support for basic vector opcodes

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 ++ tcg/riscv/tcg-target.c.inc | 52 ++ tcg/riscv/tcg-target.h | 2 +- 3 files changed, 55 insertions

Re: [PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

On 2024/9/10 12:34, Richard Henderson wrote: On 9/9/24 19:46, LIU Zhiwei wrote:     lmul = type - riscv_lg2_vlenb;     if (lmul < -3) {     /* Host VLEN >= 1024 bits. */     vlmul = VLMUL_M1; I am not sure if we should use VLMUL_MF8, Perhaps.  See below.     } else if (lm

Re: [PATCH v3 05/14] tcg/riscv: Implement vector load/store

On 2024/9/5 14:39, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: @@ -811,31 +849,52 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)   tcg_out_ext32s(s, ret, arg);   }   -static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data

Re: [PATCH v3 00/14] Add support for vector

On 2024/9/6 7:46, Alistair Francis wrote: On Thu, Sep 5, 2024 at 12:29 AM LIU Zhiwei wrote: From: TANG Tiancheng Can you please mention RISC-V in the cover letter title. Otherwise it's not obvious that this is RISC-V specific Sorry. I miss it. Thanks, Zhiwei Alistair This patc

Re: [PATCH v3 03/14] tcg/riscv: Add basic support for vector

On 2024/9/5 12:05, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each

Re: [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo

On 2024/9/9 23:45, Richard Henderson wrote: On 9/9/24 00:18, LIU Zhiwei wrote: On 2024/9/5 11:34, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: +    if (info & CPUINFO_ZVE64X) { +    /* + * Get vlenb for Vector: vsetvli rd, x0, e64. + * VLMAX = LMUL *

Re: [PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

On 2024/9/5 14:03, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction:    1. Sets the vector length (vl) in bytes    2. Configures the vtype

Re: [PATCH v3 08/14] tcg/riscv: Implement vector cmp ops

On 2024/9/5 15:12, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: @@ -2322,6 +2411,51 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,   riscv_set_vec_config_vl(s, type);   tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);   break; +    case

Re: [PATCH v3 06/14] tcg/riscv: Implement vector mov/dup{m/i}

On 2024/9/5 14:56, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: @@ -698,6 +704,21 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)   case TCG_TYPE_I64:   tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);   break; +    case

Re: [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo

On 2024/9/5 11:34, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: +    if (info & CPUINFO_ZVE64X) { +    /* + * Get vlenb for Vector: vsetvli rd, x0, e64. + * VLMAX = LMUL * VLEN / SEW. + * The "vsetvli rd, x0, e64" means "LMU

Re: [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops

On 2024/9/5 3:05, Richard Henderson wrote: On 9/4/24 08:25, LIU Zhiwei wrote: I'm trying to work out how much benefit there is here of expanding these early, as opposed to simply using TCG_REG_TMP0 when the immediate doesn't fit, We find for rotli,  it just copied cod

Re: [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops

On 2024/9/3 23:15, Richard Henderson wrote: On 8/29/24 23:16, LIU Zhiwei wrote: @@ -2589,6 +2605,69 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,   }   }   break; +    case INDEX_op_shli_vec: +    if (a2 >

[PATCH v3 14/14] tcg/riscv: Enable native vector support for TCG host

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 082942d858..099b7aa705 100644

[PATCH v3 13/14] tcg/riscv: Implement vector roti/v/x shi ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 86 +- tcg/riscv/tcg-target.h | 8 ++-- 3 files changed, 90 insertions(+), 5 deletions(-) diff --git

[PATCH v3 12/14] tcg/riscv: Implement vector shs/v ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 44 ++ tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/tcg

[PATCH v3 11/14] tcg/riscv: Implement vector min/max ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 + tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg

[PATCH v3 10/14] tcg/riscv: Implement vector sat/mul ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv

[PATCH v3 09/14] tcg/riscv: Implement vector neg ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 7 +++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg

[PATCH v3 08/14] tcg/riscv: Implement vector cmp ops

x27;s cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 3 + tcg/riscv/tcg-target-con-str.h | 2 + tcg/riscv/tcg-target.c.inc

[PATCH v3 06/14] tcg/riscv: Implement vector mov/dup{m/i}

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 53 ++ 1 file changed, 53 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index

[PATCH v3 07/14] tcg/riscv: Add support for basic vector opcodes

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 46 ++ tcg/riscv/tcg-target.h | 2 +- 3 files changed, 48 insertions(+), 1 deletion(-) diff --git a

[PATCH v3 05/14] tcg/riscv: Implement vector load/store

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target.c.inc | 202 +++-- 2 files changed, 196 insertions(+), 8 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg

[PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

: Weiwei Li Reviewed-by: Liu Zhiwei --- include/tcg/tcg.h | 3 + tcg/riscv/tcg-target.c.inc | 128 + 2 files changed, 131 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 21d5884741..267e6ff95c 100644 --- a/include/tcg/tcg.h

[PATCH v3 03/14] tcg/riscv: Add basic support for vector

ff-by: TANG Tiancheng Co-authored-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 166 ++--- tcg/riscv/tcg-target.h | 78 +--- tcg/riscv/tcg-target.opc.h | 12 +++ 4

[PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo

stead. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- host/include/riscv/host/cpuinfo.h | 3 +++ util/cpuinfo-riscv.c | 26 -- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv

[PATCH v3 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation

compare with immediate and scalar operand) Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/tcg-op-gvec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0308732d9b..78ee1ced80 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg

[PATCH v3 00/14] Add support for vector

From: TANG Tiancheng This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets. v3: 1. Use the .insn form in cpuinfo probing. 2. Use reserved_regs to constrain the register group index instead of using constrain. 3. Avoid using macros to imp

[PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index eb5129a976..b8f553207e 100644 --- a/tcg/riscv/tcg-target.h

[PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 98 +- tcg/riscv/tcg-target.h | 8 ++-- tcg/riscv/tcg-target.opc.h | 3 ++ 3 files changed, 104 insertions(+), 5 deletions(-) diff --git a/tcg

[PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 44 ++ tcg/riscv/tcg-target.h | 4 ++-- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git

[PATCH v2 11/14] tcg/riscv: Implement vector min/max ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 29 + tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg

[PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg

[PATCH v2 09/14] tcg/riscv: Implement vector neg ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 8 tcg/riscv/tcg-target.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1e8c0fb031

[PATCH v2 08/14] tcg/riscv: Implement vector cmp ops

x27;s cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 6 +- tcg/riscv/tcg-target.c.inc | 240 + tcg/riscv/tcg-target.

[PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 ++ tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 54 ++ tcg/riscv/tcg-target.h | 2 +- 4 files changed, 58

[PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i}

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 54 ++ 1 file changed, 54 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6f8814564a..b6b4bdc269 100644

[PATCH v2 05/14] tcg/riscv: Implement vector load/store

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target.c.inc | 169 - 2 files changed, 167 insertions(+), 4 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg

[PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support

: Weiwei Li Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 104 + 1 file changed, 104 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 5ef1538aed..49d01b8775 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg

[PATCH v2 03/14] tcg/riscv: Add basic support for vector

ff-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 131 + tcg/riscv/tcg-target.h | 78 +++- tcg/riscv/tcg-target.opc.h | 12 +++ 4 files changed, 157 insertions(+

[PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo

stead. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- host/include/riscv/host/cpuinfo.h | 2 ++ util/cpuinfo-riscv.c | 26 -- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv

[PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation

compare with immediate and scalar operand) Reviewed-by: Liu Zhiwei --- tcg/tcg-op-gvec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0308732d9b..78ee1ced80 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3939,7 +3939,7

[PATCH v2 00/14] tcg/riscv: Add support for vector

From: TANG Tiancheng This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets. v2: 1. Remove [PATCH v1 03/15] and use a simpler approach with fixed constraints at initialization in the backend instead of modifying register allocation constraints i

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