[PATCH v3 14/19] target/riscv: Add Zvksh ISA extension support

Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 4 +- target/riscv/cpu.h | 1 + target/riscv/helper.h| 3 + target/riscv/insn32.decode | 4 + target/riscv

[PATCH v3 13/19] target/riscv: Add Zvknh ISA extension support

/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Lawrence Hunter Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 + target/riscv/helper.h

[PATCH v3 18/19] target/riscv: Add Zvksed ISA extension support

From: Max Chou This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.

[PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts

From: Dickon Hood Rotates have been fixed up to only allow for reasonable rotate amounts (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv vector rotate instructions. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson --- include/qemu/bitops.h | 24

[PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 42

[PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction

From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson ---

[PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support

-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 7 ++ target/riscv/cpu.h | 1 + target/riscv/helper.h| 6 ++ target/riscv

[PATCH v3 15/19] target/riscv: Add Zvkg ISA extension support

-authored-by: Lawrence Hunter Signed-off-by: Lawrence Hunter Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 5 +- target/riscv/cpu.h | 1 + target/riscv/helper.h| 3 + target/riscv/insn32.decode | 4

[PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk ---

[PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks

From: Nazar Kazakov Remove the redundant "vl == 0" check which is already included within the vstart >= vl check, when vl == 0. Signed-off-by: Nazar Kazakov --- target/riscv/insn_trans/trans_rvv.c.inc | 31 + 1 file changed, 1 insertion(+), 30 deletions(-) diff

[PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops

From: Nazar Kazakov This commit adds helper functions and tcg operation definitions for the andcs and rotrs instructions Signed-off-by: Nazar Kazakov --- accel/tcg/tcg-runtime-gvec.c | 11 +++ accel/tcg/tcg-runtime.h | 1 + include/tcg/tcg-op-gvec.h| 4

[PATCH v3 12/19] target/riscv: Add Zvkned ISA extension support

/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter Co-authored-by: William Salmon Signed-off-by: Lawrence Hunter Signed-off-by: William Salmon Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 6

[PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support

From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in

[PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties

From: Nazar Kazakov Exposes earlier CPU flags allowing the use of the vector cryptography extensions. Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b754d7e13b..2f71d612725

[PATCH v3 05/19] target/riscv: Move vector translation checks

From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by: Richard Henderson ---

[PATCH v3 16/19] crypto: Create sm4_subword

From: Max Chou Allows sharing of sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Reviewed-by: Richard Henderson --- include/crypto/sm4.h | 8 target/arm/tcg/crypto_helper.c | 10 ++ 2 files changed, 10 insertions(+), 8

[PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers

From: Kiran Ostrolenk This is for use in the RISC-V vclz and vctz instructions (implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 54 +++ 1 file changed, 54 insertions(+) diff

[PATCH v3 17/19] crypto: Add SM4 constant parameter CK

From: Max Chou Adds sm4_ck constant for use in sm4 cryptography across different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index

[PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support

Lawrence Hunter (2): target/riscv: Add Zvbc ISA extension support target/riscv: Add Zvksh ISA extension support Max Chou (3): crypto: Create sm4_subword crypto: Add SM4 constant parameter CK target/riscv: Add Zvksed ISA extension support Nazar Kazakov (6): target/riscv: Remove

[PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro

From: Kiran Ostrolenk Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Reviewed-by: Alistair

[PATCH v2 13/17] target/riscv: Add Zvkg ISA extension support

-authored-by: Lawrence Hunter Signed-off-by: Lawrence Hunter Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 5 +- target/riscv/cpu.h | 1 + target/riscv/helper.h| 3 + target/riscv/insn32.decode | 4

[PATCH v2 10/17] target/riscv: Add Zvkned ISA extension support

/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter Co-authored-by: William Salmon Signed-off-by: Lawrence Hunter Signed-off-by: William Salmon Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 6

[PATCH v2 11/17] target/riscv: Add Zvknh ISA extension support

/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Lawrence Hunter Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 + target/riscv/helper.h

[PATCH v2 08/17] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers

From: Kiran Ostrolenk This is for use in the RISC-V vclz and vctz instructions (implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk --- include/qemu/host-utils.h | 54 +++ 1 file changed, 54 insertions(+) diff --git

[PATCH v2 04/17] target/riscv: Move vector translation checks

From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov --- target/riscv/insn_trans/trans_rvv.c.inc | 28

[PATCH v2 17/17] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b754d7e13b..2f71d612725 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1485,6 +1485,16 @@ static

[PATCH v2 12/17] target/riscv: Add Zvksh ISA extension support

Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 4 +- target/riscv/cpu.h | 1 + target/riscv/helper.h| 3 + target/riscv/insn32.decode | 4 + target/riscv

[PATCH v2 14/17] crypto: Create sm4_subword

From: Max Chou - Share sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- include/crypto/sm4.h | 8 target/arm/tcg/crypto_helper.c | 10 ++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git

[PATCH v2 09/17] target/riscv: Add Zvbb ISA extension support

From: Dickon Hood This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vswll.[vv,vx,vi] Translation functions are defined in

[PATCH v2 03/17] target/riscv: Add Zvbc ISA extension support

-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 7 ++ target/riscv/cpu.h | 1 + target/riscv/helper.h| 6 ++ target/riscv

[PATCH v2 06/17] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 42

[PATCH v2 15/17] crypto: Add SM4 constant parameter CK

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c78..2987306cf7a 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@

[PATCH v2 01/17] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk ---

[PATCH v2 05/17] target/riscv: Refactor translation of vector-widening instruction

From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood ---

[PATCH v2 16/17] target/riscv: Add Zvksed ISA extension support

From: Max Chou This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.

[PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro

From: Kiran Ostrolenk Factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk --- target/riscv/insn_trans/trans_rvv.c.inc | 62

[PATCH v2 07/17] qemu/bitops.h: Limit rotate amounts

From: Dickon Hood Rotates have been fixed up to only allow for reasonable rotate amounts (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv vector rotate instructions. Signed-off-by: Dickon Hood --- include/qemu/bitops.h | 24 1 file changed, 16

[PATCH v2 00/17] Add RISC-V vector cryptographic instruction set support

integers target/riscv: Add Zvknh ISA extension support Lawrence Hunter (2): target/riscv: Add Zvbc ISA extension support target/riscv: Add Zvksh ISA extension support Max Chou (3): crypto: Create sm4_subword crypto: Add SM4 constant parameter CK target/riscv: Add Zvksed ISA extension support

Re: [PATCH 00/45] Add RISC-V vector cryptographic instruction set support

On 21/03/2023 12:02, Christoph Müllner wrote: On Fri, Mar 10, 2023 at 10:16 AM Lawrence Hunter wrote: This patchset provides an implementation for Zvkb, Zvkned, Zvknh, Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the 20230303 version of the specification

Re: [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality

On 21/03/2023 12:02, Christoph Müllner wrote: On Fri, Mar 10, 2023 at 5:06 PM Lawrence Hunter wrote: From: Kiran Ostrolenk Summary of refactoring: * take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals` * factor the non SEW-specific stuff

[PATCH 39/45] target/riscv: Add vghsh.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkg.c.inc | 10 ++ target/riscv/vcrypto_helper.c | 38 ++ 4 files changed, 50 insertions

[PATCH 41/45] crypto: Create sm4_subword

From: Max Chou - Share sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- include/crypto/sm4.h | 8 target/arm/tcg/crypto_helper.c | 10 ++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git

[PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support

Co-authored-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvksh.c.inc | 37 +++ target/riscv

[PATCH 36/45] target/riscv: Expose zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e218a00a2d..c136a17112 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1486,6 +1486,7 @@ static Property

[PATCH 40/45] target/riscv: Expose zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 79079d517d..323e0c462b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1484,6 +1484,7 @@ static Property riscv_cpu_extensions

[PATCH 43/45] target/riscv: Add zvksed cfg property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 323e0c462b..84a225bf5f 100644 --- a/target/riscv/cpu.c +++

[PATCH 44/45] target/riscv: Add Zvksed support

From: Max Chou - add vsm4k, vsm4r instructions Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hun...@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kaza...@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor

[PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkg.c.inc | 30 +++ target/riscv/translate.c

[PATCH 33/45] target/riscv: Add zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 4 +++- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3f9638067..e218a00a2d 100644 --- a/target/riscv/cpu.c +++

[PATCH 42/45] crypto: Add SM4 constant parameter CK

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3

[PATCH 31/45] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 2 + target/riscv/vcrypto_helper.c

[PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support

From: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 82 +

[PATCH 37/45] target/riscv: Add zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c136a17112..79079d517d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7

[PATCH 32/45] target/riscv: Expose zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3ffbdd53cc..b3f9638067 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1482,6 +1482,8 @@ static Property

[PATCH 45/45] target/riscv: Expose Zvksed property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 84a225bf5f..8caa485f28 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1489,6 +1489,7 @@ static

[PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 38 ++ target/riscv/vcrypto_helper.c | 21 4

[PATCH 16/45] target/riscv: Add zvkned cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 462615140c..00e1d007a4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 35/45] target/riscv: Add vsm3c.vi decoding, translation and execution support

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvksh.c.inc | 6 ++ target/riscv/vcrypto_helper.c | 95 + 4 files

[PATCH 24/45] target/riscv: Add vaesem.vv decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 17 + 4 files

[PATCH 14/45] target/riscv: Add vandn.[vv, vx] decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- accel/tcg/tcg-runtime-gvec.c | 11 +++ accel/tcg/tcg-runtime.h| 1 + target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2 ++

[PATCH 06/45] target/riscv: Add vclmulh.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 13 + 4 files changed, 16 insertions(+) diff --git

[PATCH 22/45] target/riscv: Add vaesdm.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 4 4 files changed, 7 insertions(+) diff --git

[PATCH 08/45] target/riscv: Refactor some of the generic vector functionality

From: Nazar Kazakov Moves the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commit without check duplication. Signed-off-by: Nazar Kazakov --- target/riscv/insn_trans/trans_rvv.c.inc | 28

[PATCH 18/45] target/riscv: Add vaesef.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 20 +++ target/riscv/vcrypto_helper.c| 36 4 files changed, 58

[PATCH 20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 3 +++ 4 files changed, 6 insertions(+) diff --git

[PATCH 28/45] target/riscv: Expose zvkned cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 00e1d007a4..cd87eec919 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1472,6 +1472,7 @@ static Property

[PATCH 26/45] target/riscv: Add vaeskf1.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 58 target/riscv/vcrypto_helper.c| 44

[PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 11 +++ 4 files changed, 17

[PATCH 04/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 46 -

[PATCH 09/45] qemu/bitops.h: Limit rotate amounts

From: Dickon Hood Rotates have been fixed up to only allow for reasonable rotate amounts (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv vector rotate instructions. Signed-off-by: Dickon Hood --- include/qemu/bitops.h | 24 1 file changed, 16

[PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 48 ++ target/riscv

[PATCH 25/45] target/riscv: Add vaesem.vs decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 3 +++ 4 files changed, 6

[PATCH 00/45] Add RISC-V vector cryptographic instruction set support

Lawrence Hunter (17): target/riscv: Add vclmul.vv decoding, translation and execution support target/riscv: Add vclmul.vx decoding, translation and execution support target/riscv: Add vclmulh.vv decoding, translation and execution support target/riscv: Add vclmulh.vx decoding

[PATCH 21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 36 4 files changed, 39 insertions

[PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support

From: Dickon Hood Add an implementation of the vrol.* and vror.* instructions, with mappings between the RISC-V instructions and their internal TCG accelerated implmentations. There are some missing ror helpers, so I've bodged it by converting them to rols. Co-authored-by: Nazar Kazakov

[PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 3 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzvkned.c.inc | 72 +++ target/riscv

[PATCH 19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 31 4 files changed, 34 insertions

[PATCH 11/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 39

[PATCH 23/45] target/riscv: Add vaesz.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 2 ++ 4 files changed, 5 insertions(+) diff --git

[PATCH 15/45] target/riscv: Expose zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69611408f9..462615140c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1469,6 +1469,9 @@ static Property

[PATCH 01/45] target/riscv: Add zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 13 + target/riscv/cpu.h | 1 + 2 files changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..69611408f9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 02/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Summary of refactoring: * take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals` * factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`) All this refactoring

[PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/target/riscv

[PATCH 29/45] target/riscv: Add zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 11 ++- target/riscv/cpu.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd87eec919..3ffbdd53cc 100644 --- a/target/riscv/cpu.c +++

[PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 13 + target/riscv/vcrypto_helper.c| 59 4

[PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkb.c.inc

[PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support

From: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 82 +

[PATCH 33/45] target/riscv: Add zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 4 +++- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3f9638067..e218a00a2d 100644 --- a/target/riscv/cpu.c +++

[PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkg.c.inc | 30 +++ target/riscv/translate.c

[PATCH 42/45] crypto: Add SM4 constant parameter CK

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3

[PATCH 41/45] crypto: Create sm4_subword

From: Max Chou - Share sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- include/crypto/sm4.h | 8 target/arm/tcg/crypto_helper.c | 10 ++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git

[PATCH 39/45] target/riscv: Add vghsh.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkg.c.inc | 10 ++ target/riscv/vcrypto_helper.c | 38 ++ 4 files changed, 50 insertions

[PATCH 36/45] target/riscv: Expose zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e218a00a2d..c136a17112 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1486,6 +1486,7 @@ static Property

[PATCH 45/45] target/riscv: Expose Zvksed property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 84a225bf5f..8caa485f28 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1489,6 +1489,7 @@ static

[PATCH 43/45] target/riscv: Add zvksed cfg property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 323e0c462b..84a225bf5f 100644 --- a/target/riscv/cpu.c +++

[PATCH 44/45] target/riscv: Add Zvksed support

From: Max Chou - add vsm4k, vsm4r instructions Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hun...@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kaza...@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor

[PATCH 40/45] target/riscv: Expose zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 79079d517d..323e0c462b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1484,6 +1484,7 @@ static Property riscv_cpu_extensions

[PATCH 37/45] target/riscv: Add zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c136a17112..79079d517d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7

[PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support

Co-authored-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvksh.c.inc | 37 +++ target/riscv

[PATCH 31/45] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 2 + target/riscv/vcrypto_helper.c

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