[PATCH 35/45] target/riscv: Add vsm3c.vi decoding, translation and execution support

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvksh.c.inc | 6 ++ target/riscv/vcrypto_helper.c | 95 + 4 files c

[PATCH 32/45] target/riscv: Expose zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3ffbdd53cc..b3f9638067 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1482,6 +1482,8 @@ static Property riscv

[PATCH 01/45] target/riscv: Add zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 13 + target/riscv/cpu.h | 1 + 2 files changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..69611408f9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@

[PATCH 15/45] target/riscv: Expose zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69611408f9..462615140c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1469,6 +1469,9 @@ static Property risc

[PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 11 +++ 4 files changed, 17 inser

[PATCH 19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 31 4 files changed, 34 insertions

[PATCH 22/45] target/riscv: Add vaesdm.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 4 4 files changed, 7 insertions(+) diff --git a

[PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 13 + target/riscv/vcrypto_helper.c| 59 4 files

[PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 3 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzvkned.c.inc | 72 +++ target/riscv

[PATCH 00/45] Add RISC-V vector cryptographic instruction set support

: Add vsha2ms.vv decoding, translation and execution support target/riscv: Add zvksh cpu property target/riscv: Add vsm3c.vi decoding, translation and execution support target/riscv: Expose zvksh cpu property Lawrence Hunter (17): target/riscv: Add vclmul.vv decoding, translation and

[PATCH 18/45] target/riscv: Add vaesef.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 20 +++ target/riscv/vcrypto_helper.c| 36 4 files changed, 58

[PATCH 28/45] target/riscv: Expose zvkned cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 00e1d007a4..cd87eec919 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1472,6 +1472,7 @@ static Property riscv_c

[PATCH 09/45] qemu/bitops.h: Limit rotate amounts

From: Dickon Hood Rotates have been fixed up to only allow for reasonable rotate amounts (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv vector rotate instructions. Signed-off-by: Dickon Hood --- include/qemu/bitops.h | 24 1 file changed, 16 i

[PATCH 02/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Summary of refactoring: * take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals` * factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`) All this refactoring ensu

[PATCH 08/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Also moves the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the function

[PATCH 20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 3 +++ 4 files changed, 6 insertions(+) diff --git a

[PATCH 16/45] target/riscv: Add zvkned cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 462615140c..00e1d007a4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support

From: Dickon Hood Add an implementation of the vrol.* and vror.* instructions, with mappings between the RISC-V instructions and their internal TCG accelerated implmentations. There are some missing ror helpers, so I've bodged it by converting them to rols. Co-authored-by: Nazar Kazakov Signed

[PATCH 25/45] target/riscv: Add vaesem.vs decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 3 +++ 4 files changed, 6 insertions(

[PATCH 29/45] target/riscv: Add zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 11 ++- target/riscv/cpu.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd87eec919..3ffbdd53cc 100644 --- a/target/riscv/cpu.c +++ b/target/

[PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 48 ++ target/riscv

[PATCH 26/45] target/riscv: Add vaeskf1.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 58 target/riscv/vcrypto_helper.c| 44 ++

[PATCH 24/45] target/riscv: Add vaesem.vv decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 17 + 4 files chan

[PATCH 14/45] target/riscv: Add vandn.[vv, vx] decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- accel/tcg/tcg-runtime-gvec.c | 11 +++ accel/tcg/tcg-runtime.h| 1 + target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/tr

[PATCH 23/45] target/riscv: Add vaesz.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 2 ++ 4 files changed, 5 insertions(+) diff --git a

[PATCH 06/45] target/riscv: Add vclmulh.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 13 + 4 files changed, 16 insertions(+) diff --git

[PATCH 11/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 39 target/riscv/vector_in

[PATCH 21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 36 4 files changed, 39 insertions

[PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkb.c.inc

[PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 38 ++ target/riscv/vcrypto_helper.c | 21 4

[PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/target/riscv

[PATCH 04/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 36 - target/riscv/vector_i

[PATCH 27/39] target/riscv: expose zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a78d9ae120..5076699226 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1092,6 +1092,8 @@ static Property riscv

[PATCH 10/39] target/riscv: expose zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bd34119c75..35790befc0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1082,6 +1082,8 @@ static Property riscv

[PATCH 20/39] target/riscv: Add vaesem.vs decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 3 +++ 4 files changed, 6 insertions(+)

[PATCH 38/39] target/riscv: Add Zvksed support

From: Max Chou - add vsm4k, vsm4r instructions Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hun...@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kaza...@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor s

[PATCH 14/39] target/riscv: Add vaesdf.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 31 + 4 files changed, 34 insertions

[PATCH 21/39] target/riscv: Add vaeskf1.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 45 + target/riscv/vcrypto_helper.c | 42 +

[PATCH 32/39] target/riscv: add zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a3b08e9d27..6fded328f8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,7

[PATCH 19/39] target/riscv: Add vaesem.vv decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 17 + 4 files changed,

[PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Co-authored-by: Kiran Ostrolenk Co-authored-by: Max Chou Signed-off-by: Max Chou Signed-off-by: Kiran Ostrolenk Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 3 + target/riscv/insn32.decode

[PATCH 39/39] target/riscv: Expose Zvksed property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0fa7049c3b..a4e8347d5f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1100,6 +1100,7 @@ static

[PATCH 15/39] target/riscv: Add vaesdf.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 3 +++ 4 files changed, 6 insertions(+) diff --git a/target

[PATCH 18/39] target/riscv: Add vaesz.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 13 - target/riscv/vcrypto_helper.c | 2 ++ 4 files changed, 12 insertions(+), 5

[PATCH 00/39] Add RISC-V vector cryptography extensions

/riscv: Add vsm3c.vi decoding, translation and execution support target/riscv: expose zvksh cpu property Lawrence Hunter (16): target/riscv: Add vclmul.vv decoding, translation and execution support target/riscv: Add vclmul.vx decoding, translation and execution support target/riscv: Add

[PATCH 01/39] target/riscv: add zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 12 target/riscv/cpu.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..bd34119c75 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@

[PATCH 17/39] target/riscv: Add vaesdm.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 4 4 files changed, 7 insertions(+) diff --git a/target

[PATCH 34/39] target/riscv: expose zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fded328f8..48701e118f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1095,6 +1095,7 @@ static Property riscv_cpu_extensions

[PATCH 08/39] target/riscv: Add vrev8.v decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 10 ++ 4 files changed, 16 insert

[PATCH 28/39] target/riscv: add zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 4 +++- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5076699226..9a412d9d53 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/c

[PATCH 09/39] target/riscv: Add vandn.[vv, vx, vi] decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 9 + target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 5 + target/riscv/vcrypto_helper.c | 19 +++ 4 file

[PATCH 03/39] target/riscv: Add vclmul.vx decoding, translation and execution support

Co-authored-by: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans

[PATCH 04/39] target/riscv: Add vclmulh.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 12 4 files changed, 15 insertions(+) diff --git

[PATCH 23/39] target/riscv: expose zvkns cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd09822b4f..0da04d0be1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1084,6 +1084,7 @@ static Property riscv_c

[PATCH 16/39] target/riscv: Add vaesdm.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 36 + 4 files changed, 39 insertions

[PATCH 22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 9 target/riscv/vcrypto_helper.c | 56 + 4 files cha

[PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzvkns.c.inc | 40 +++ target/riscv/translate.c

[PATCH 36/39] crypto: Add SM4 constant parameter CK.

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3

[PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 2 + target/riscv/vcrypto_helper.c

[PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv

From: Max Chou - Share SM4_SBOXWORD between target/riscv and target/arm. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- include/crypto/sm4.h | 7 +++ target/arm/crypto_helper.c | 10 ++ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/crypto/

[PATCH 13/39] target/riscv: Add vaesef.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 16 + target/riscv/vcrypto_helper.c | 38 + 4 files changed, 56

[PATCH 30/39] target/riscv: Add vsm3c.vi decoding, translation and execution support

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvksh.c.inc | 8 ++ target/riscv/vcrypto_helper.c | 90 + 4 files c

[PATCH 31/39] target/riscv: expose zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9a412d9d53..a3b08e9d27 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1097,6 +1097,7 @@ static Property ris

[PATCH 11/39] target/riscv: add zvkns cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 35790befc0..fd09822b4f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 37/39] target/riscv: Add zvksed cfg property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 48701e118f..0fa7049c3b 100644 --- a/target/riscv/cpu.c +++ b/tar

[PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkg.c.inc | 9 + target/riscv/translate.c

[PATCH 24/39] target/riscv: add zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0da04d0be1..a78d9ae120 100644 --- a/target/riscv/cpu.c +++ b/target/r

[PATCH 05/39] target/riscv: Add vclmulh.vx decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 12 4 files changed, 15 insertions(+) diff --git

[PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support

From: Dickon Hood Add an initial implementation of the vrol.* and vror.* instructions, with mappings between the RISC-V instructions and their internal TCG accelerated implmentations. There are some missing ror helpers, so I've bodged it by converting them to rols. Co-authored-by: Kiran Ostrole

[PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support

Co-authored-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvksh.c.inc | 12 ++ target/riscv/translate.c

[PATCH 07/39] target/riscv: Add vbrev8.v decoding, translation and execution support

From: William Salmon Co-authored-by: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: William Salmon --- include/qemu/bitops.h | 32 + target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 1 + targ

[PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support

From: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 45 target/ris

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