[PATCH] target/i386: Introduce SapphireRapids-v3 to add missing features

Add the missing features(ss, tsc-adjust, cldemote, movdiri, movdir64b) in the SapphireRapids-v3 CPU model. Signed-off-by: Lei Wang --- target/i386/cpu.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fd6af0d763..77e7945152 100644

[PATCH] migration: Yield coroutine when receiving MIG_CMD_POSTCOPY_LISTEN

bug harder to be reproduced. Fix this by yielding the load coroutine when receiving MIG_CMD_POSTCOPY_LISTEN so the main event loop can handle the connection event before loading the non-iterative devices state to avoid the deadlock condition. Signed-off-by: Lei Wang --- migration/savevm.c | 5 +

[PATCH] multifd: Set a higher "backlog" default value for listen()

set later on and a high number of channels are used. Set it to a hard-coded higher default value 512 to fix this issue. Reported-by: Wei Wang Signed-off-by: Lei Wang --- migration/socket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migration/socket.c b/migration/socket.

[PATCH v3 5/6] i386: Initialize AMX CPUID leaves with corresponding env->features[] leaves

off-by: Lei Wang --- target/i386/cpu.c | 27 +-- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e638a31d34..946df29a3d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -576,16 +576,16 @@ static CPUCacheI

[PATCH v3 4/6] i386: Mask and report unavailable multi-bit feature values

, and delegating this responsibility can let each multi-bit feature have its own way to mask bits. Signed-off-by: Lei Wang --- target/i386/cpu-internal.h | 2 ++ target/i386/cpu.c | 36 2 files changed, 38 insertions(+) diff --git a/target/i386/cpu-internal.h b

[PATCH v3 1/6] i386: Introduce FeatureWordInfo for AMX CPUID leaf 0x1D and 0x1E

CPUID leaf 0x1D and 0x1E enumerate tile and TMUL information for AMX. Introduce FeatureWord FEAT_1D_1_EAX, FEAT_1D_1_EBX, FEAT_1D_1_ECX and FEAT_1E_0_EBX. Thus these features of AMX can be expanded when "-cpu host/max" and can be configured in named CPU model. Signed-off-by

[PATCH v3 0/6] Support for new CPU model SapphireRapids

-1-lei4.w...@intel.com/T/#t Lei Wang (6): i386: Introduce FeatureWordInfo for AMX CPUID leaf 0x1D and 0x1E i386: Remove unused parameter "uint32_t bit" in feature_word_description() i386: Introduce new struct "MultiBitFeatureInfo" for multi-bit features i

[PATCH v3 2/6] i386: Remove unused parameter "uint32_t bit" in feature_word_description()

Parameter "uint32_t bit" is not used in function feature_word_description(), so remove it. Signed-off-by: Lei Wang --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b6d1247e5e..883098bc5a 100644 --

[PATCH v3 3/6] i386: Introduce new struct "MultiBitFeatureInfo" for multi-bit features

rdInfo, so that the infomation can be assigned for each item in feature_word_info array and used in the future. Signed-off-by: Lei Wang --- target/i386/cpu-internal.h | 9 +++ target/i386/cpu.c | 54 ++ 2 files changed, 63 insertions(+) diff --git a/t

[PATCH v3 6/6] i386: Add new CPU model SapphireRapids

in future versions: - fast zero-length MOVSB (KVM doesn't support yet) - fast short STOSB (KVM doesn't support yet) - fast short CMPSB, SCASB (KVM doesn't support yet) Signed-off-by: Lei Wang Reviewed-by: Robert Hoo --- target/i386/cpu.c | 135 ++ target