> On Wed, Jul 24, 2024 at 10:09 AM Lei Wang wrote:
> > Because the index value of the VMCS field encoding of Secondary
> > VM-exit controls, 0x44, is larger than any existing index value, raise
> > the highest index value used for any VMCS encoding to 0x44.
> >
> > Because the index value of the V
On 7/6/2024 9:23 AM, Paolo Bonzini wrote:
>
>
> Il sab 6 lug 2024, 17:57 Li, Xin3 <mailto:xin3...@intel.com>> ha scritto:
>
> >> The bits in the secondary vmexit controls are not supported, and
> in general the same
> >> is true for the s
>> The bits in the secondary vmexit controls are not supported, and in general
>> the same
>> is true for the secondary vmexit case. I think it's better to not include
>> the vmx-entry-
>> load-fred bit either, and only do the vmxcap changes.
> Right, we don't need it at all.
Hi Paolo,
We act
> The bits in the secondary vmexit controls are not supported, and in general
> the same
> is true for the secondary vmexit case. I think it's better to not include
> the vmx-entry-
> load-fred bit either, and only do the vmxcap changes.
Right, we don't need it at all.
>
> Also, in patch 1 th
> > > NULL, NULL, NULL, NULL, @@ -1552,6 +1552,14 @@ static
> > > FeatureDep feature_dependencies[] = {
> > > .from = { FEAT_VMX_SECONDARY_CTLS,
> VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE },
> > > .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG },
> > >
>> @@ -1552,6 +1552,14 @@ static FeatureDep feature_dependencies[] = {
>> .from = { FEAT_VMX_SECONDARY_CTLS,
>> VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE },
>> .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG },
>> },
>> +{
>> +.from = { FEAT_7_1_EAX
> > FRED CPU states are managed in 10 FRED MSRs, in addtion to a few
> > existing CPU registers and MSRs, e.g., the CR4.FRED bit.
> >
> > Add the 10 new FRED MSRs to x86 CPUArchState for live migration support.
> >
>
> IMO, it's better to split this patch into two, one is for FRED MSR access,
> t
