[PATCH] cxl: Get rid of unused cfmw_list

There is no user for this member. All '-M cxl-fmw.N' options have been parsed and saved to CXLState.fixed_windows. Signed-off-by: Li Zhijian --- hw/cxl/cxl-host.c| 1 - include/hw/cxl/cxl.h | 1 - 2 files changed, 2 deletions(-) diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index c5f5f

[PATCH v2 3/3] migration/colo: Tidy up bql_unlock() around bdrv_activate_all()

Make the code more tight. Suggested-by: Michael Tokarev Reviewed-by: Peter Xu Reviewed-by: Zhang Chen Signed-off-by: Li Zhijian --- V2: Collected reviewed-by tags This change/comment suggested by "Michael Tokarev " came a bit late at that time, let's update it together in these minor set this

[PATCH v2 2/3] migration/colo: make colo_incoming_co() return void

Currently, it always returns 0, no need to check the return value at all. In addition, enter colo coroutine only if migration_incoming_colo_enabled() is true. Once the destination side enters the COLO* state, the COLO process will take over the remaining processes until COLO exits. Cc: Fabiano Ros

[PATCH v2 1/3] migration/colo: Minor fix for colo error message

- Explicitly show the missing module name: replication - Fix capability name to x-colo Reviewed-by: Peter Xu Reviewed-by: Zhang Chen Signed-off-by: Li Zhijian --- V2: Collected reviewed-by tags --- migration/migration.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/

[PATCH 2/3] migration/colo: make colo_incoming_co() return void

Currently, it always returns 0, no need to check the return value at all. In addition, enter colo coroutine only if migration_incoming_colo_enabled() is true. Once the destination side enters the COLO* state, the COLO process will take over the remaining processes until COLO exits. Signed-off-by:

[PATCH 3/3] migration/colo: Tidy up bql_unlock() around bdrv_activate_all()

Make the code more tight. Cc: Michael Tokarev Signed-off-by: Li Zhijian --- This change/comment suggested by "Michael Tokarev " came a bit late at that time, let's update it together in these minor set this time. --- migration/colo.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff

[PATCH 1/3] migration/colo: Minor fix for colo error message

- Explicitly show the missing module name: replication - Fix capability name to x-colo Signed-off-by: Li Zhijian --- migration/migration.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/migration/migration.c b/migration/migration.c index 6502e169a3..b4a09c561c 100644 -

[PATCH] backends/cryptodev-builtin: Fix local_error leaks

It seems that this error does not need to be propagated to the upper, directly output the error to avoid the leaks Closes: https://gitlab.com/qemu-project/qemu/-/issues/2283 Signed-off-by: Li Zhijian --- backends/cryptodev-builtin.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-)

[PATCH v2] migration/colo: Fix bdrv_graph_rdlock_main_loop: Assertion `!qemu_in_coroutine()' failed.

bdrv_activate_all() should not be called from the coroutine context, move it to the QEMU thread colo_process_incoming_thread() with the bql_lock protected. The backtrace is as follows: #4 0x561af7948362 in bdrv_graph_rdlock_main_loop () at ../block/graph-lock.c:260 #5 0x561af7907a68 i

[PATCH] migration/colo: Fix bdrv_graph_rdlock_main_loop: Assertion `!qemu_in_coroutine()' failed.

bdrv_activate_all() should not be called from the coroutine context, move it to the QEMU thread colo_process_incoming_thread() with the bql_lock protected. The backtrace is as follows: #4 0x561af7948362 in bdrv_graph_rdlock_main_loop () at ../block/graph-lock.c:260 #5 0x561af7907a68 i

[PATCH v2] hw/mem/cxl_type3: reset dvsecs in ct3d_reset()

After the kernel commit 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window") CXL type3 devices cannot be enabled again after the reboot because the control register(see 8.1.3.2 in CXL specifiction 2.0 for more details) was not reset. These registers coul

[PATCH 1/2] CXL/cxl_type3: add first_dvsec_offset() helper

It helps to figure out where the first dvsec register is located. In addition, replace offset and size hardcore with existing macros. Signed-off-by: Li Zhijian --- hw/mem/cxl_type3.c | 19 +-- 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/

[PATCH 2/2] CXL/cxl_type3: reset DVSEC CXL Control in ct3d_reset

After the kernel commit 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window") CXL type3 devices cannot be enabled again after the reboot because this flag was not reset. This flag could be changed by the firmware or OS, let it have a reset(default) value

[PATCH] migration, docs: mark RDMA migration as deprecated

Except for RDMA migration, other parts of the RDMA subsystem have been removed since 9.1. Due to the lack of unit tests and CI tests for RDMA migration, int the past developing cycles, a few fatal errors were introduced and broke the RDMA migration, and these issues[1][2] were not fixed until some