I'm starting to doubt my diagnosis. The bug may be in my understanding of
the interrupt priorities. I'll have to do another test program.
On Oct 11, 2015 11:25 AM, "Peter Crosthwaite"
wrote:
> On Fri, Oct 9, 2015 at 6:28 AM, Michael Davidsaver
> wrote:
> > Han
Implement the SYSRESETREQ bit of the AIRCR register
for armv7-m (ie. cortex-m3) to trigger a GPIO out.
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index
Add GPIO in for the stellaris board which calls
qemu_system_reset_request() on reset request.
Signed-off-by: Michael Davidsaver
---
hw/arm/stellaris.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 82a4ad5..0114e0a 100644
--- a/hw
Change armv7m_init to return the DeviceState* for the NVIC.
This allows access to all GPIO blocks, not just the IRQ inputs.
Move qdev_get_gpio_in() calls out of armv7m_init() into
board code for stellaris and stm32f205 boards.
Signed-off-by: Michael Davidsaver
---
hw/arm/armv7m.c| 9
On 10/11/2015 11:23 AM, Peter Crosthwaite wrote:
> On Fri, Oct 9, 2015 at 6:28 AM, Michael Davidsaver
> wrote:
>> The M series MPU is almost the same as the already
>> implemented R series MPU. So use the M series
>> and translate as best we can.
>>
> There i
Change armv7m_init to return the DeviceState* for the NVIC.
This allows access to all GPIO blocks, not just the IRQ inputs.
Move qdev_get_gpio_in() calls out of armv7m_init() into
board code for stellaris and stm32f205 boards.
---
hw/arm/armv7m.c| 9 ++---
hw/arm/stellaris.c | 29
Add GPIO in for the stellaris board which calls
qemu_system_reset_request() on reset request.
---
hw/arm/stellaris.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 82a4ad5..0114e0a 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellar
board installs a handler which calls
qemu_system_reset_request().
Michael Davidsaver (3):
armv7-m: Return DeviceState* from armv7m_init()
armv7-m: Implement SYSRESETREQ
arm: stellaris: exit on external reset request
hw/arm/armv7m.c| 9 ++---
hw/arm/stellaris.c | 41
Implement the SYSRESETREQ bit of the AIRCR register
for armv7-m (ie. cortex-m3) to trigger a GPIO out.
---
hw/intc/armv7m_nvic.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 3ec8408..6fc167e 100644
--- a/hw/intc/arm
Give an explicit error and abort when a load
from VECBASE fails. Otherwise would likely
jump to 0, which for v7-m holds the reset stack
pointer address.
Signed-off-by: Michael Davidsaver
---
target-arm/helper.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a
For -M These should always be thumb mode.
Log a message if this is seen.
Signed-off-by: Michael Davidsaver
---
target-arm/helper.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4408100..4178400 100644
--- a/target
Add CPU unassigned access handler in place of special
MemoryRegion to catch exception returns.
Signed-off-by: Michael Davidsaver
---
hw/arm/armv7m.c | 8
target-arm/cpu.c | 18 ++
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm
ector # with sub-group as per tie breaking rules.
NVIC now derives directly from SysBusDevice, and
struct NVICClass is eliminated.
Also add DPRINTF() macro.
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 74 ++-
target-arm/cpu.h
qtest, but can't quite see how to use it given the need to
execute code to test most of the exception behavior. Is something like this
feasible at present?
Regards,
Michael
Michael Davidsaver (18):
armv7m: MRS/MSR handle unprivileged access
armv7m: Undo armv7m.hack
armv7m: Com
The MRS and MSR instruction handling isn't checking
the current permission level.
Signed-off-by: Michael Davidsaver
---
target-arm/helper.c | 79 +
1 file changed, 37 insertions(+), 42 deletions(-)
diff --git a/target-arm/helper.c b/t
The polarity is reversed, and it should include
internal exceptions.
Should be set when # of active exceptions <= 1.
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b
armv7m_nvic.c no longer relies on the GIC.
Remove REV_NVIC and conditionals which use it.
Signed-off-by: Michael Davidsaver
---
hw/intc/arm_gic.c| 14 +++---
hw/intc/arm_gic_common.c | 23 ---
hw/intc/gic_internal.h | 7 ++-
3 files changed, 17
Internal functions for operations previously done
by GIC internals.
nvic_irq_update() recalculates highest pending/active
exceptions.
armv7m_nvic_set_pending() include exception escalation
logic.
armv7m_nvic_acknowledge_irq() and nvic_irq_update()
update ARMCPU fields.
Signed-off-by: Michael
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 64 +--
1 file changed, 62 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 3b10dee..c860b36 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw
No need to bounce through EXCP_IRQ handling
for non-IRQ exceptions. just update CPU
state directly.
Signed-off-by: Michael Davidsaver
---
target-arm/helper.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index
Prevent unprivileged from writing to the
Software Triggered Interrupt register
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ca8c93c..b744cd5 100644
--- a/hw
Replace use of GIC state/functions with new NVIC.
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 233 --
1 file changed, 168 insertions(+), 65 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ebb4d4e
pending exception
can interrupt execution.
Signed-off-by: Michael Davidsaver
---
target-arm/cpu.c | 26 +++---
target-arm/cpu.h | 27 ++-
2 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index be026bc
on return from all exceptions other than NMI
Signed-off-by: Michael Davidsaver
---
target-arm/helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5be09b8..83af528 100644
--- a/target-arm/helper.c
+++ b/target-arm
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 107 --
1 file changed, 51 insertions(+), 56 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index c860b36..8eaf677 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw
Implement Configuration and Control register.
Handle STACKALIGN and USERSETMPEND bits.
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 15 +++
target-arm/cpu.h | 1 +
target-arm/helper.c | 8 +++-
target-arm/machine.c | 1 +
4 files changed, 16
Add the Configurable and Hard Fault Status registers.
Note undefined instructions and escalations
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 10 +++---
target-arm/cpu.h | 2 ++
target-arm/helper.c | 1 +
target-arm/machine.c | 6 --
4 files changed, 14
Detect use of reserved exception return codes
and return to thread mode from nested
exception handler.
Also check consistency between NVIC and CPU
wrt. the active exception.
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 7 +++-
target-arm/cpu.h | 2 +-
target-arm
On 11/18/2015 02:41 PM, Peter Maydell wrote:
> For a big patchset like this the easiest thing is to just ask
> Michael if he has a public git repo with the patches in (I've
> cc'd him).
https://github.com/mdavidsaver/qemu/tree/fixirq
The posted patches were
https://github.com/qemu/qemu/compare/c
On 04/06/2016 06:23 PM, Liviu Ionescu wrote:
>
>> On 07 Apr 2016, at 01:04, Peter Maydell wrote:
>>
>> ... Somebody needs to do the necessary work to fix the
>> code review issues. ...
>
> in this case I'll probably wait for this process to be completed and
> reevaluate the situation by then.
On 11/20/2015 08:59 AM, Peter Maydell wrote:
> I think I've now done that at least for the earlier patches.
> There are probably some other finer details that I'll get to
> in a later round of patch review but hopefully you have enough
> to do some of the fixes and restructuring of this patchset fo
On 11/17/2015 12:09 PM, Peter Maydell wrote:
> On 9 November 2015 at 01:11, Michael Davidsaver wrote:
>> The MRS and MSR instruction handling isn't checking
>> the current permission level.
>>
>> Signed-off-by: Michael Davidsaver
>
On 11/17/2015 12:20 PM, Peter Maydell wrote:
> This one's not really correct, I'm afraid (though the spec-mandated
> behaviour is a bit subtle).
I've dropped this patch.
On 11/17/2015 12:33 PM, Peter Maydell wrote:
> On 9 November 2015 at 01:11, Michael Davidsaver wrote:
>> Give an explicit error and abort when a load
>> from VECBASE fails. Otherwise would likely
>> jump to 0, which for v7-m holds the reset stack
>> pointer a
On 11/17/2015 01:10 PM, Peter Maydell wrote:
> On 9 November 2015 at 01:11, Michael Davidsaver wrote:
>> Expand the NVIC to fully support -M priorities and masking.
>> Doesn't use GIC code.
>>
>> Move some state to ARMCPU to allow calculation of exception masking
On 11/20/2015 08:25 AM, Peter Maydell wrote:
> On 9 November 2015 at 01:11, Michael Davidsaver wrote:
>> Internal functions for operations previously done
>> by GIC internals.
>>
>> nvic_irq_update() recalculates highest pending/active
>> exceptions.
>&g
On 11/17/2015 12:58 PM, Peter Maydell wrote:
> On 9 November 2015 at 01:11, Michael Davidsaver wrote:
>> Signed-off-by: Michael Davidsaver
>> ---
>> hw/intc/armv7m_nvic.c | 64
>> +--
>> 1 file chang
On 11/20/2015 08:47 AM, Peter Maydell wrote:
> On 9 November 2015 at 01:11, Michael Davidsaver wrote:
>> Despite having the same notation, these bits
>> have completely different meaning than -AR.
>>
>> Add armv7m_excp_unmasked()
>> to calculate the currently run
Track priorities and highest active and pending
exception. Also the highest pending exception
for faster exception handler entry.
The pending exception information will be re-calculated
on load, so no additional vmstate tracking is needed.
---
target-arm/cpu.c | 2 ++
target-arm/cpu.h | 3 +++
2
Add CPU unassigned access handler in place of special
MemoryRegion to catch exception returns.
The unassigned handler will signal other faults as either
prefetch or data exceptions, with the FSR code 0x8 to
distinguish them from memory translation faults (0xd).
Future code will make use of this di
No need to bounce through EXCP_IRQ handling
for non-IRQ exceptions. just update CPU
state directly.
---
target-arm/helper.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7b76f32..4490b74 100644
--- a/target-arm/he
The MRS and MSR instruction handling isn't checking
the current permission level.
Prevent privlaged from changing writing EPSR fields.
Access to unknown/undefined special registers not
fatal (read 0, write ignored) w/ guest error message.
---
target-arm/helper.c | 79 +
Give an explicit error and abort when a load
from VECBASE fails. Otherwise would likely
jump to 0, which for v7-m holds the reset stack
pointer address.
---
target-arm/helper.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-a
Add the Configurable, HardFault, BusFault and MemManage Status registers.
Note undefined instructions, violations, and escalations.
No BusFaults are raised at this point.
---
hw/intc/armv7m_nvic.c | 28 ++--
target-arm/cpu.h | 4
target-arm/helper.c | 3 +++
ge size will probably break most unmodified guests using the MPU. I can't
see any way around this short of changes to the TLB code, or a seperate build
with TARGET_PAGE_BITS==5. I'm not inclined to undertake either.
Should this part of the series be dropped?
Michael
[1] https://github.
Despite having the same notation, these bits
have completely different meaning than -AR.
Use armv7m_excp_running_prio() and the highest
pending exception priority to determine
if the pending exception can interrupt preempt.
---
target-arm/cpu.c | 16 ++--
1 file changed, 6 insertions(
Implements v7m exception priority algorithm
using FAULTMASK, PRIMASK, BASEPRI, and the highest
priority active exception.
The number returned is the current execution priority
which may be in the range [-2,0x7f] when an exception is active
or 0x100 when no exception is active.
---
hw/intc/armv7m_
Detect use of reserved exception return codes
and return to thread mode from nested
exception handler.
Also check consistency between NVIC and CPU
wrt. the active exception.
---
hw/intc/armv7m_nvic.c | 7 +++-
target-arm/cpu.h | 2 +-
target-arm/helper.c | 95
armv7m_nvic.c no longer relies on the GIC.
Remove REV_NVIC and conditionals which use it.
---
hw/intc/arm_gic.c| 14 +++---
hw/intc/arm_gic_common.c | 23 ---
hw/intc/gic_internal.h | 7 ++-
3 files changed, 17 insertions(+), 27 deletions(-)
diff --git a
on return from all exceptions other than NMI
---
target-arm/helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d1ca011..b6ec761 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5379,8 +5379,13 @@ static v
At least for TI TM4C1294.
LR==-1
XPSR==0
PRIMASK, FAULTMASK, and BASEPRI all cleared
so exception handlers are unmasked.
STKALIGN set.
---
target-arm/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1fa1f96..8b85888 100644
---
Update MPU background policy as per ARM.
Main changes are preventing writes to ROM
and no-exec for device regions.
---
target-arm/helper.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e73f7a
Prevent unprivileged from writing to the
Software Triggered Interrupt register
---
hw/intc/armv7m_nvic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 0f9ca6a..5731146 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv
Expand the NVIC to fully support -M priorities and masking.
Doesn't use GIC code.
Use PRIGROUP to configure group/sub-group split.
Track group and sub-group in separate fields for quick comparison.
Mix in vector # with sub-group as per tie breaking rules.
NVIC now derives directly from SysBusDevi
Always pass these through to be caught be by the
unassigned handler.
---
target-arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e42f6d0..a5adf2d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7106,6 +7106,15
cpu_generic_init() without realized=true.
Gives board code an opportunity to change
CPU properties.
---
include/qom/cpu.h | 12
qom/cpu.c | 23 +--
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 5
The ARM states that this bit indicates the stack
being used, which in handler mode is always MSP.
Further CONTROL<1>==1 in handler mode is reserved.
With the TM4C always CONTROL<1>==0 in handler mode
which inconveniently prevents the handler from
knowing which stack thread mode was using...
This
Implement Configuration and Control register.
Handle STACKALIGN and USERSETMPEND bits.
---
hw/intc/armv7m_nvic.c | 15 +++
target-arm/cpu.h | 1 +
target-arm/helper.c | 8 +++-
target-arm/machine.c | 1 +
4 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw
cpu_reset() is called as a side-effect
of realizing the CPU.
arm_cpu_reset() calls rom_ptr(0), which
expects to find the image mapped.
This was happening way before load_*()
and was worked around with a second call to cpu_reset().
Now wait to realize until after the image is mapped.
---
hw/arm/arm
Many v7m CPUs don't implement all of the 8 bits
of the priority fields. Typically, only the
top N bits are available. Existing practice
implies that writes to unimplemented
bits will be ignore, and read as zero.
This allows a guest to discover the implemented
bits by writing 0xff to (eg. basepri
Set an appropriate FSR code when an access does
not match any MPU region, including the background/default.
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index da99825..e73f7a6 100644
--- a/target-arm/helper.c
The M series MPU is almost the same as the already
implemented R series MPU. So use the M series
and translate.
Primary difference is that a real v7-M MPU is has
much relaxed alignment and size requirements for MPU
regions (32 bytes) compared with the 1K page size
of the QEMU TLB which is shared
Provide some more "-d mmu" related to the MPU translation
process as an aid in debugging guest MPU configurations.
Helpful since our MPU resolution is limited to the ARM7-AR
page size.
---
target-arm/helper.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/
General logic is that operations stopped by the MPU are MemManage,
and those which go through the MPU and are caught by the unassigned
handle are BusFault.
---
target-arm/helper.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/target-arm/he
Separate init and realize phases to allow
board code the opportunity to set properties
on the cpu and nvic.
Assign names for cpu, nvic, and bitband regions.
update stellaris and stm32 board code accordingly.
---
hw/arm/armv7m.c| 42 +++---
hw/arm/stell
On 12/17/2015 10:38 AM, Peter Maydell wrote:
> On 3 December 2015 at 00:18, Michael Davidsaver wrote:
>> Add CPU unassigned access handler in place of special
>> MemoryRegion to catch exception returns.
>>
>> The unassigned handler will signal other faults as either
>
On 12/17/2015 08:25 AM, Peter Maydell wrote:
> On 3 December 2015 at 00:18, Michael Davidsaver wrote:
>> ...
>> +static
>> +uint32_t arm_v7m_load_vector(ARMCPU *cpu)
>> +
>> +{
>> +CPUState *cs = &cpu->parent_obj;
> This isn't the righ
On 12/17/2015 09:36 AM, Peter Maydell wrote:
> On 3 December 2015 at 00:18, Michael Davidsaver wrote:
>> Implements v7m exception priority algorithm
>> using FAULTMASK, PRIMASK, BASEPRI, and the highest
>> priority active exception.
>>
>> The number returned
On 12/17/2015 10:38 AM, Peter Maydell wrote:
> We could use a comment here (a) explaining what we're doing and (b)
> mentioning that this isn't architecturally correct -- ideally we should
> catch these exception exits on execution of the jump insn, not by
> letting the jump execute and then trappi
On 12/17/2015 10:18 AM, Peter Maydell wrote:
> On 17 December 2015 at 14:39, Peter Maydell wrote:
>> On 3 December 2015 at 00:18, Michael Davidsaver
>> wrote:
>>> Despite having the same notation, these bits
>>> have completely different meaning than -AR.
>
On 02/16/2017 09:11 AM, Peter Maydell wrote:
> I haven't actually checked real hardware behaviour, but I think
> we can fairly safely implement this as not checking the IPSR
> exception field. (We might as well go with the "reads 1 in
> handler mode" choice of UNKNOWN that the M3 documents, though.
On 02/18/2017 01:38 PM, Peter Maydell wrote:
> On 18 February 2017 at 17:45, Michael Davidsaver
> wrote:
>> On 02/16/2017 09:11 AM, Peter Maydell wrote:
>>> I haven't actually checked real hardware behaviour, but I think
>>> we can fairly safely impl
101 - 172 of 172 matches
Mail list logo
