I'm working on a port to a new architecture and was noticing a discrepancy in
where the disassembler code lives. There is a file "target//disas.c" for
4 architectures (avr, loongarch, openrisc, and rx), but a file "disas/.c"
for 14 architectures (if I counted right). It seems the 4 architectur
Richard,
It's been 6 months so I thought I'd check in again. Do you have an estimate
of when this will go in?
Michael
-Original Message-----
From: Michael Morrell
Sent: Wednesday, July 14, 2021 10:50 AM
To: 'Richard Henderson' ; qemu-devel@nongnu.org
Subje
OK, thanks for the update. I also appreciate you looking at the NaN issue.
Michael
-Original Message-
From: Richard Henderson
Sent: Wednesday, July 14, 2021 9:57 AM
To: Michael Morrell ; qemu-devel@nongnu.org
Subject: Re: [PATCH 03/11] softfloat: Introduce float_flag_inorm_denormal
Just curious. What's the expected timeline to get these denormal patches in
the tree?
-Original Message-
From: Richard Henderson
Sent: Saturday, May 29, 2021 8:21 AM
To: Michael Morrell ; qemu-devel@nongnu.org
Cc: alex.ben...@linaro.org
Subject: Re: [PATCH 03/11] softfloat: Intr
t;denorm / 0" or any instruction
with a NaN operand, float_flag_inorm_denormal should not be set (and that way,
the DE bit in MXCSR won't be set when it shouldn't be).
Michael
-Original Message-
From: Michael Morrell
Sent: Monday, June 21, 2021 5:57 PM
To: 'Richard Hender
.
Michael
-Original Message-
From: Richard Henderson
Sent: Monday, June 21, 2021 4:30 PM
To: Michael Morrell ; qemu-devel@nongnu.org
Subject: Re: Denormal input handling
On 6/21/21 4:13 PM, Michael Morrell wrote:
> I have another couple of thoughts around input denormal handling.
>
, June 21, 2021 4:30 PM
To: Michael Morrell ; qemu-devel@nongnu.org
Subject: Re: Denormal input handling
On 6/21/21 4:13 PM, Michael Morrell wrote:
> I have another couple of thoughts around input denormal handling.
>
> The first is straightforward. I noticed that the Aarch64 port doesn'
I have another couple of thoughts around input denormal handling.
The first is straightforward. I noticed that the Aarch64 port doesn't report
input denormals (I could not find any code which sets the IDC bit in the FPSR).
I found code in the arm (not aarch64) port that sets other bits like IX
single flag
combined with the "flush_inputs_to_zero" flag to accomplish what the two
separate "input denormal" flags do?
Michael
-Original Message-
From: Richard Henderson
Sent: Wednesday, May 26, 2021 9:14 PM
To: qemu-devel@nongnu.org
Cc: Michael Morrell ; alex.ben...@lina
.
Richard, are you willing to make the change or do you want me to try?
Thanks,
Michael
-Original Message-
From: Peter Maydell
Sent: Wednesday, May 26, 2021 1:19 PM
To: Michael Morrell
Cc: qemu-devel@nongnu.org; Richard Henderson
Subject: Re: Denormal input handling
On Wed, 26 May
to the ARM documentation?
Michael
On Wednesday, May 26, 2021, 12:28:38 PM PDT, Richard Henderson
wrote:
On 5/26/21 12:23 PM, Richard Henderson wrote:
> On 5/26/21 12:02 PM, Michael Morrell via wrote:
>> I think the behavior should be for denormal inputs that if
>> "
I see support in QEMU for architectures which have a denormal input flag bit
and those that have a "flush inputs to zero" control bit, but the
implementation is not specializable and seems wrong for x86 at least.
For example, in sf_canonicalize, if the input is denormal and
"flush_inputs_to_zer
I see support in QEMU for architectures which have a denormal input flag bit
and those that have a "flush inputs to zero" control bit, but the
implementation is not specializable and seems wrong for x86 at least.
For example, in sf_canonicalize, if the input is denormal and
"flush_inputs_to_zer
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