Re: [Qemu-devel] [PATCH 1/7] target/mips: compare virtual addresses in LL/SC sequence

ann; Laurent Vivier; Paolo Bonzini; Peter Maydell; Philippe Mathieu-Daudé; Richard Henderson; Riku Voipio; Yongbok Kim; Aleksandar Markovic; Goran Ferenc; Miodrag Dinic; Petar Jovanovic Subject: Re: [PATCH 1/7] target/mips: compare virtual addresses in LL/SC sequence Aleksandar Marko

[Qemu-devel] [PATCH] target/mips: fix msa copy_[s|u]_df rd = 0 corner case

From: Miodrag Dinic <miodrag.di...@imgtec.com> This patch fixes the msa copy_[s|u]_df instruction emulation when the destination register rd is zero. Without this patch the zero register would get clobbered, which should never happen because it is supposed to be hardwired to 0. Fix this

Re: [Qemu-devel] [PATCH v2] target-mips: Fix ALIGN instruction when bp=0

Thanks Leon, I'll make sure future patches are sent inline. Regards, Miodrag From: Leon Alrae Sent: Friday, January 08, 2016 5:09 PM To: Miodrag Dinic; Aurelien Jarno Cc: qemu-devel@nongnu.org; Petar Jovanovic Subject: Re: [Qemu-devel] [PATCH v2] target

[Qemu-devel] [PATCH v2] target-mips: Fix ALIGN instruction when bp=0

gards, Miodrag From: Aurelien Jarno [aurel...@aurel32.net] Sent: Friday, January 01, 2016 2:02 PM To: Miodrag Dinic Cc: qemu-devel@nongnu.org; Petar Jovanovic Subject: Re: [PATCH] target-mips: Fix ALIGN instruction when bp=0 [snip] > From e01539a11061c447bece8dccde1715da9534024d Mon Sep 17 00:

[Qemu-devel] [PATCH] target-mips: Fix ALIGN instruction when bp=0

ser/qemu-mips64el -cpu MIPS64R6-generic ./align-instr-test ALIGN PASS: Expected = fedcba98, actual = fedcba98 DALIGN PASS: Expected = fedcba98, actual = fedcba98 ALIGN PASS: Expected = 1234567, actual = 1234567 DALIGN PASS: Expected = 1234567, actual = 1234567 ALIGN PASS: Expected =