Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

On Wed, 21 Nov 2018 14:01:10 PST (-0800), alistai...@gmail.com wrote: On Wed, Nov 21, 2018 at 1:37 PM Palmer Dabbelt wrote: On Wed, 21 Nov 2018 11:21:40 PST (-0800), alistai...@gmail.com wrote: > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe wrote: >> >> >> >&

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

On Wed, 21 Nov 2018 11:21:40 PST (-0800), alistai...@gmail.com wrote: On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe wrote: On 2018-11-21 12:16 p.m., Alistair Francis wrote: >>> Do you see the MicroSemi PCIe probe in your dmesg? >> >> I do when I have a kernel with microsemi PCI Support

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistai...@gmail.com wrote: On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe wrote: On 2018-11-21 10:02 a.m., Alistair Francis wrote: > Connect the Xilinx PCIe device based on the information in the device > tree stored in the ROM of the HiFish

Re: [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions

On Tue, 20 Nov 2018 17:15:11 PST (-0800), alistai...@gmail.com wrote: On Fri, Nov 16, 2018 at 12:33 AM Richard Henderson wrote: On 11/15/18 11:35 PM, Alistair Francis wrote: > +static void reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) > +{ > +intptr_t offset =

[Qemu-devel] No RISC-V Patches this Week

I don't have anything in my patch queue for this week, so I don't plan on sending a pull request. Let me know if I'm missing anything.

[Qemu-devel] [PULL 4/4] RISC-V: Respect fences for user-only emulators

-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f44eb9c41b48..312bf298b3c2 100644 --- a/target/riscv/translate.c +++ b/target

[Qemu-devel] [PULL 3/4] target/riscv: Fix sfence.vm/a both available in any priv version

From: Bastian Koppelmann sfence.vm has been replaced in priv v1.10 spec by sfence.vma. Reported-by: Richard Henderson Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 18 +- 1 file changed, 13

[Qemu-devel] [PULL] RISC-V Patches for 3.1-rc2

available in any priv version Palmer Dabbelt (1): RISC-V: Respect fences for user-only emulators hw/riscv/virt.c | 1 + target/riscv/translate.c | 24 2 files changed, 17 insertions(+), 8 deletions(-)

[Qemu-devel] [PULL 1/4] hw/riscv/virt: Free the test device tree node name

From: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a137a503c8a..2b38f890702c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -240,6 +240,7

[Qemu-devel] [PULL 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only

From: Bastian Koppelmann Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d1471d

[Qemu-devel] [PULL 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only

From: Bastian Koppelmann Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d1471d

[Qemu-devel] [PULL 1/4] hw/riscv/virt: Free the test device tree node name

From: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a137a503c8a..2b38f890702c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -240,6 +240,7

[Qemu-devel] [PULL 3/4] target/riscv: Fix sfence.vm/a both available in any priv version

From: Bastian Koppelmann sfence.vm has been replaced in priv v1.10 spec by sfence.vma. Reported-by: Richard Henderson Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 18 +- 1 file changed, 13

[Qemu-devel] [PULL 4/4] RISC-V: Respect fences for user-only emulators

-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f44eb9c41b48..312bf298b3c2 100644 --- a/target/riscv/translate.c +++ b/target

[Qemu-devel] [PR RFC] RISC-V Patches for 3.1-rc2

available in any priv version Palmer Dabbelt (1): RISC-V: Respect fences for user-only emulators hw/riscv/virt.c | 1 + target/riscv/translate.c | 24 2 files changed, 17 insertions(+), 8 deletions(-)

[Qemu-devel] [PATCH for 3.1] RISC-V: Respect fences for user-only emulators

-by: Palmer Dabbelt --- target/riscv/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d1471d..624d1c679a84 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1766,7 +1766,6 @@ static void

[Qemu-devel] [PATCH for 3.1] RISC-V: Respect fences for user-only emulators

I'd like to target this for 3.1: while it's a pretty esoteric bug the risk of breaking anything is low and tracking down a manifestation of the bug would be a nightmare. I don't think the performance improvement alluded to will be a 3.1 candidiate, and as a result I probably won't get around to

Re: [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

On Fri, 09 Nov 2018 02:53:45 PST (-0800), Peter Maydell wrote: On 8 November 2018 at 18:52, Palmer Dabbelt wrote: On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistai...@gmail.com wrote: On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt wrote: The following changes since commit

Re: [Qemu-devel] [PATCH 0/2] target/riscv: Bugfixes found in decodetree conversion

On Thu, 08 Nov 2018 09:29:26 PST (-0800), Bastian Koppelmann wrote: On 11/8/18 4:53 PM, Richard Henderson wrote: On 11/8/18 1:06 PM, Bastian Koppelmann wrote: while going through the reviews of the riscv-decodetree patches, two bugs came up that I fix here. There is one more problem [1]

Re: [Qemu-devel] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name

e(nodename); > > nodename = g_strdup_printf("/uart@%lx", > (long)memmap[VIRT_UART0].base); > -- > 2.19.1 > Reviewed-by: Palmer Dabbelt

Re: [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistai...@gmail.com wrote: On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt wrote: The following changes since commit a7ce790a029bd94eb320d8c69f38900f5233997e: tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +) are available

Re: [Qemu-devel] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name

On Thu, 08 Nov 2018 10:37:28 PST (-0800), alistai...@gmail.com wrote: On Wed, Nov 7, 2018 at 6:38 PM Palmer Dabbelt wrote: On Wed, 07 Nov 2018 13:51:45 PST (-0800), Alistair Francis wrote: > Signed-off-by: Alistair Francis > --- > hw/riscv/virt.c | 1 + > 1 file changed,

[Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

The following changes since commit a7ce790a029bd94eb320d8c69f38900f5233997e: tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +) are available in the Git repository at: git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1 for you to fetch changes up to

[Qemu-devel] [PULL] riscv: spike: Fix memory leak in the board init

Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/spike.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 8a712ed49026..268df04c3c7d 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,9 +316,7 @@ static

Re: [Qemu-devel] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name

On Wed, 07 Nov 2018 13:51:45 PST (-0800), Alistair Francis wrote: Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a137a503c..2b38f89070 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -240,6

Re: [Qemu-devel] List of files containing devices which have not been QOMified

On Tue, 06 Nov 2018 10:43:17 PST (-0800), Peter Maydell wrote: I had an idea for how to get a rough list of source files containing devices that haven't been QOMified. The theory is that a pre-QOM device generally has an "init" function which allocates memory for the device struct. So looking in

Re: [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding

On Mon, 05 Nov 2018 09:00:10 PST (-0800), Bastian Koppelmann wrote: On 11/1/18 4:59 PM, Palmer Dabbelt wrote: On Wed, 31 Oct 2018 15:38:08 PDT (-0700), richard.hender...@linaro.org wrote: On 10/31/18 1:20 PM, Bastian Koppelmann wrote:  static bool trans_slt(DisasContext *ctx, arg_slt

Re: [Qemu-devel] [PATCH v1 1/1] riscv: spike: Fix memory leak in the board init

wed-by: Palmer Dabbelt

[Qemu-devel] [PULL 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

h the high bits of the CSR being wrong. Signed-off-by: Dayeol Lee Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index f4

[Qemu-devel] [PULL 3/3] Add qemu-ri...@nongnu.org as the RISC-V list

We now have a RISC-V specific QEMU development list. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index

[Qemu-devel] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2

maintainer, and one to add our newly created mailing list. Dayeol Lee (1): target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 Palmer Dabbelt (2): Add Alistair as a RISC-V Maintainer Add qemu-ri...@nongnu.org

[Qemu-devel] [PULL 2/3] Add Alistair as a RISC-V Maintainer

Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d794bd7a66fe..d550fd8b809c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -241,6 +241,7 @@ F: disas/ppc.c RISC-V M: Michael Clark M: Palmer Dabbelt +M: Alistair Francis M: Sagar

Re: [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding

On Wed, 31 Oct 2018 15:38:08 PDT (-0700), richard.hender...@linaro.org wrote: On 10/31/18 1:20 PM, Bastian Koppelmann wrote: static bool trans_slt(DisasContext *ctx, arg_slt *a) { -gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2); +TCGv source1 = tcg_temp_new(); +TCGv source2 =

Re: [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree

On Wed, 31 Oct 2018 03:44:27 PDT (-0700), Bastian Koppelmann wrote: On 10/20/18 9:14 AM, Bastian Koppelmann wrote: [...] +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn) +{ +#if defined(TARGET_RISCV64) +REQUIRE_FPU; + +TCGv t0 = tcg_temp_new(); +

Re: [Qemu-devel] [PULL 2/3] Add Alistair as a RISC-V Maintainer

On Tue, 30 Oct 2018 14:33:23 PDT (-0700), alistai...@gmail.com wrote: On Tue, Oct 30, 2018 at 2:23 PM Palmer Dabbelt wrote: Alistair has been contributing to the RISC-V QEMU port for a while now so I'd like him to be officially listed as a maintainer. I've checked with the other RISC-V

[Qemu-devel] [PR RFC] RISC-V Patches for the 3.1 Soft Freeze, Part 2

): target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 Palmer Dabbelt (2): Add Alistair as a RISC-V Maintainer Add qemu-ri...@nongnu.org as the RISC-V list MAINTAINERS| 2 ++ target/riscv/pmp.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)

[Qemu-devel] [PULL 3/3] Add qemu-ri...@nongnu.org as the RISC-V list

We now have a RISC-V specific QEMU development list. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index

[Qemu-devel] [PULL 2/3] Add Alistair as a RISC-V Maintainer

Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d794bd7a66fe..d550fd8b809c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -241,6 +241,7 @@ F: disas/ppc.c RISC-V M: Michael Clark M: Palmer Dabbelt +M: Alistair Francis M: Sagar

[Qemu-devel] [PULL 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

h the high bits of the CSR being wrong. Signed-off-by: Dayeol Lee Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index f4

[Qemu-devel] [PATCH] Add qemu-ri...@nongnu.org as the RISC-V list

We now have a RISC-V specific QEMU development list. Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d550fd8b809c..10983bd52d64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -244,6 +244,7 @@ M: Palmer Dabbelt M

Re: [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

ogus on RV64I, with the high bits of the CSR being wrong. > > Signed-off-by: Dayeol Lee > Reviewed-by: Palmer Dabbelt > --- > target/riscv/pmp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index c82

Re: [Qemu-devel] [PATCH] Add Alistair as a RISC-V Maintainer

On Mon, 29 Oct 2018 10:59:47 PDT (-0700), Peter Maydell wrote: On 29 October 2018 at 17:14, Palmer Dabbelt wrote: I don't think we have anything ready to go right now: your PCIe patches still have some outstanding feedback (on interrupt stuff), and Bastian's decodetree stuff has some patches

Re: [Qemu-devel] [PATCH] Add Alistair as a RISC-V Maintainer

On Mon, 29 Oct 2018 09:48:30 PDT (-0700), alistai...@gmail.com wrote: On Mon, Oct 29, 2018 at 9:44 AM Philippe Mathieu-Daudé wrote: On 29/10/18 17:16, Palmer Dabbelt wrote: > Alistair has been contributing to the RISC-V QEMU port for a while now > so I'd like him to be officially

Re: [Qemu-devel] [PATCH] Add Alistair as a RISC-V Maintainer

On Mon, 29 Oct 2018 09:30:54 PDT (-0700), phi...@redhat.com wrote: On 29/10/18 17:16, Palmer Dabbelt wrote: Alistair has been contributing to the RISC-V QEMU port for a while now so I'd like him to be officially listed as a maintainer. I've checked with the other RISC-V mainatiners

[Qemu-devel] [PATCH] Add Alistair as a RISC-V Maintainer

Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d794bd7a66fe..d550fd8b809c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -241,6 +241,7 @@ F: disas/ppc.c RISC-V M: Michael Clark M: Palmer Dabbelt +M: Alistair Francis M: Sagar

Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree

On Fri, 26 Oct 2018 03:53:11 PDT (-0700), kbast...@mail.uni-paderborn.de wrote: On 10/25/18 12:21 AM, Palmer Dabbelt wrote: On Sat, 20 Oct 2018 00:14:22 PDT (-0700), kbast...@mail.uni-paderborn.de wrote: Hi, this patchset converts the RISC-V decoder to decodetree in three major steps: 1

Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC

On Fri, 26 Oct 2018 07:53:17 PDT (-0700), Bastian Koppelmann wrote: On 10/26/18 3:58 PM, Richard Henderson wrote: On 10/26/18 11:49 AM, Bastian Koppelmann wrote: I think you can pick up everything up to the RVC conversion which still needs the work suggested by Richard. Thanks, for picking it

Re: [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree

;opcode), rd, rs1, imm); -break; -case OPC_RISC_BRANCH: -gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, - GET_B_IMM(ctx->opcode)); - break; case OPC_RISC_LOAD: gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); break; Reviewed-by: Palmer Dabbelt

Re: [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext

On Thu, 25 Oct 2018 09:54:56 PDT (-0700), Peter Maydell wrote: On 25 October 2018 at 17:38, Palmer Dabbelt wrote: On Sat, 20 Oct 2018 00:14:23 PDT (-0700), kbast...@mail.uni-paderborn.de wrote: CPURISCVState is rarely used, so there is no need to pass it to every translate function

Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC

asContext *ctx) } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; -decode_RV32_64G(ctx->env, ctx); +if (!decode_insn32(ctx, ctx->opcode)) { +/* fallback to old decoder */ +decode_RV32_64G(ctx->env, ctx); +} } } Rev

Re: [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext

On Sat, 20 Oct 2018 00:14:23 PDT (-0700), kbast...@mail.uni-paderborn.de wrote: CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Signed-off-by: Bastian Koppelmann

Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree

On Sat, 20 Oct 2018 00:14:22 PDT (-0700), kbast...@mail.uni-paderborn.de wrote: Hi, this patchset converts the RISC-V decoder to decodetree in three major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-14]: Many of the gen_* functions are called by the decode functions for

Re: [Qemu-devel] [PATCH 16/28] target/riscv: Convert quadrant 1 of RVXC insns to decodetree

On Fri, 19 Oct 2018 08:28:38 PDT (-0700), kbast...@mail.uni-paderborn.de wrote: On 10/13/18 8:53 PM, Richard Henderson wrote: On 10/12/18 10:30 AM, Bastian Koppelmann wrote: +static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a, uint16_t insn) +{ +if (a->imm == 0) { +return

Re: [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic insns to decodetree

On Fri, 19 Oct 2018 04:00:33 PDT (-0700), kbast...@mail.uni-paderborn.de wrote: Hi Richard, On 10/12/18 8:46 PM, Richard Henderson wrote: On 10/12/18 10:30 AM, Bastian Koppelmann wrote: +static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn) +{ +gen_arith_imm(ctx,

Re: [Qemu-devel] [RFC v3 51/56] riscv: acquire the BQL in cpu_has_work

On Thu, 18 Oct 2018 18:06:20 PDT (-0700), c...@braap.org wrote: Soon we will call cpu_has_work without the BQL. Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota --- target/riscv/cpu.c | 21 - 1 file changed

Re: [Qemu-devel] [RFC v3 16/56] riscv: convert to cpu_halted

On Thu, 18 Oct 2018 18:05:45 PDT (-0700), c...@braap.org wrote: Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Signed-off-by: Emilio G. Cota --- target/riscv/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze

get patches to start flowing upstream. Sorry for the confusion, everyone! On Thu, Oct 18, 2018 at 1:01 PM Palmer Dabbelt wrote: On Wed, 17 Oct 2018 16:32:10 PDT (-0700), ebl...@redhat.com wrote: > On 10/17/18 4:54 PM, Palmer Dabbelt wrote: >> The following changes since commit 0

Re: [Qemu-devel] [PATCH] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read return type demotion

ion rules will result in an integer here ("i*8" is integer, which flows through) resulting in a 32-bit signed value on most hosts. That's obviously bogus on RV64I, with the high bits of the CSR being wrong. Aside from the metadata Reviewed-by: Palmer Dabbelt Thanks!

Re: [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze

On Wed, 17 Oct 2018 16:32:10 PDT (-0700), ebl...@redhat.com wrote: On 10/17/18 4:54 PM, Palmer Dabbelt wrote: The following changes since commit 09558375a634e17cea6cfbfec883ac2376d2dc7f: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging (2018-10

[Qemu-devel] [PULL 3/5] RISC-V: Update CSR and interrupt definitions

paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 6

[Qemu-devel] [PULL 5/5] RISC-V: Don't add NULL bootargs to device-tree

From: Michael Clark Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Palmer Dabbelt Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 4 +++- hw/riscv/spike.c| 6 -- hw/riscv/virt.c

[Qemu-devel] [PULL 1/5] RISC-V: Allow setting and clearing multiple irqs

Reviewed-by: Palmer Dabbelt Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 8 hw/riscv/sifive_plic.c | 4 ++-- target/riscv/cpu.h | 22 +- target/riscv/op_helper.c | 24 +++- 4 files changed

[Qemu-devel] [PULL 2/5] RISC-V: Move non-ops from op_helper to cpu_helper

-Daudé Reviewed-by: Palmer Dabbelt Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 2 +- target/riscv/{helper.c => cpu_helper.c} | 35 - target/riscv/op_helper.c| 34

[Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze

The following changes since commit 09558375a634e17cea6cfbfec883ac2376d2dc7f: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging (2018-10-16 17:42:56 +0100) are available in the Git repository at: git://github.com/riscv/riscv-qemu.git

[Qemu-devel] [PULL 4/5] RISC-V: Add missing free for plic_hart_config

From: Michael Clark Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Palmer Dabbelt Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv

Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches

On Tue, 16 Oct 2018 01:05:11 PDT (-0700), peter.mayd...@linaro.org wrote: On 15 October 2018 at 21:28, Palmer Dabbelt wrote: On Fri, 12 Oct 2018 02:34:12 PDT (-0700), peter.mayd...@linaro.org wrote: The expected patch flow for QEMU is: * original patch author posts patch to qemu-devel

Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches

On Fri, 12 Oct 2018 02:34:12 PDT (-0700), peter.mayd...@linaro.org wrote: On 11 October 2018 at 21:52, Michael Clark wrote: Peter, I have to pull in your remote wholesale. I don't cherry-pick from your tree. I think this is truly dumb. This might serve the needs of some folk running Linux but

Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches

On Thu, 11 Oct 2018 02:34:16 PDT (-0700), peter.mayd...@linaro.org wrote: On 10 October 2018 at 19:22, Palmer Dabbelt wrote: On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote: On 10 October 2018 at 18:49, Palmer Dabbelt wrote: we should really get the ball rolling

Re: [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config

On Mon, 08 Oct 2018 11:25:45 PDT (-0700), alistair.fran...@wdc.com wrote: From: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 2 ++ 1 file changed, 2

Re: [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper

Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- target/riscv/Makefile.objs | 2 +- target/riscv/{helper.c => cpu_helper.c} | 35 - target/riscv/op_helpe

Re: [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree

On Mon, 08 Oct 2018 11:25:56 PDT (-0700), alistair.fran...@wdc.com wrote: From: Michael Clark Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 4 +++- hw/riscv/spike.c| 6 -- hw/riscv/virt.c | 4

Re: [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions

. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark

Re: [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs

to riscv_cpu_update_mip. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- hw/riscv/sifive_clint.c | 8 hw/riscv/sifive_plic.c | 4 ++-- target/riscv/cpu.h | 22

Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches

On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote: On 10 October 2018 at 18:49, Palmer Dabbelt wrote: we should really get the ball rolling on our big patch backlog. Yes, please do. Softfreeze is not all that far away and I would strongly prefer not to get an enormous

Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches

On Mon, 08 Oct 2018 11:25:07 PDT (-0700), alistair.fran...@wdc.com wrote: These are some patches that I have cherry picked from Michael's RISC-V tree that are ready to be applied. Unless anyone has any comments against these I'll send a PR later this week. Michael Clark (5): RISC-V: Allow

Re: [Qemu-devel] [PATCH v2 0/3] target/riscv: use tcg_lookup_and_goto_ptr

On Fri, 31 Aug 2018 15:22:49 PDT (-0700), c...@braap.org wrote: On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: Changes wrt v1: changed patch 3 as suggested by Richard. Also added his R-b's. You can fetch this series from: https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2

Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue

On Mon, 09 Jul 2018 16:04:48 PDT (-0700), Michael Clark wrote: On Tue, Jul 10, 2018 at 9:52 AM, Alistair Francis wrote: On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab wrote: > What is the state of the sifive_u emulation? When I tried to boot a bbl > with an included kernel I get these

Re: [Qemu-devel] RISC-V platform

On Fri, 29 Jun 2018 14:20:34 PDT (-0700), alistai...@gmail.com wrote: On Fri, Jun 29, 2018 at 2:05 PM, G 3 wrote: Hi, I noticed your RISC-V patches on the mailing list and had a question that I think you may be able to answer. Has anyone defined a RISC-V platform yet? What I mean is defining

Re: [Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support to RISC-V

On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.fran...@wdc.com wrote: Alistair Francis (5): hw/riscv/virtio: Set the soc device tree node as a simple-bus hw/riscv/virt: Increase the number of interrupts hw/riscv/virt: Connect the Xilinx PCIe hw/riscv/virt: Connect a VGA PCIe device

Re: [Qemu-devel] [patches] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c

On Wed, 25 Apr 2018 16:45:13 PDT (-0700), Michael Clark wrote: Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-

Re: [Qemu-devel] [PATCH] linux-user: set minimum uname for RISC-V

On Tue, 24 Apr 2018 12:07:43 PDT (-0700), peter.mayd...@linaro.org wrote: On 24 April 2018 at 17:40, Palmer Dabbelt <pal...@sifive.com> wrote: On Tue, 24 Apr 2018 09:03:29 PDT (-0700), alex.ben...@linaro.org wrote: As support was merged into the mainline kernel at 4.15 it is unlikely

Re: [Qemu-devel] [PATCH] linux-user: set minimum uname for RISC-V

TARGET_MLOCKALL_MCL_CURRENT 1 If I understand this correctly, this will make host kernels older than 4.15.0 look like 4.15.0 when a program running in user-mode emulation on a RISC-V system? I think that's the correct thing to do, so if that's the case then feel free to add a Reviewed-b

Re: [Qemu-devel] [patches] [PATCH v1 1/1] RISC-V: Workaround for critical mstatus.FS MTTCG bug

and set mstatus.FS to initial or clean. With this workaround, mstatus.FS will always return dirty if set to a non-zero value, indicating floating point save restore is necessary, versus misreporting mstatus.FS resulting in floating point register file corruption. Cc: Palmer Dabbelt <

Re: [Qemu-devel] [PATCH v3] RISC-V: Fix riscv_isa_string memory size bug

On Thu, 22 Mar 2018 15:17:16 PDT (-0700), d...@redhat.com wrote: "Richard W.M. Jones" writes: DJ, am I remembering correctly that you tried the test case on the HiFive evaluation board and it didn't demonstrate the bug? I tested it on the vc707 board, without seeing the

Re: [Qemu-devel] Apparently fpu/softfloat.c:1374 is reachable

On Fri, 09 Mar 2018 13:49:57 PST (-0800), c...@braap.org wrote: On Fri, Mar 09, 2018 at 11:34:56 +, Michael Clark wrote: Isn't Cc'ing riscv-patches an obvious use case for using the --cc flag? (BTW You can add as many --cc's as you want, and these apply to all patches in a series.) FWIW,

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

On Thu, 08 Mar 2018 03:41:33 PST (-0800), Michael Clark wrote: On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark wrote: On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark wrote: On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell wrote: On 6

Re: [Qemu-devel] [PULL 13/13] linux-user: implement renameat2

On Tue, 23 Jan 2018 12:13:07 PST (-0800), laur...@vivier.eu wrote: Le 23/01/2018 à 20:13, Palmer Dabbelt a écrit : On Tue, 23 Jan 2018 06:48:07 PST (-0800), laur...@vivier.eu wrote: From: Andreas Schwab <sch...@suse.de> This is needed for new architectures like RISC-V which do not provi

Re: [Qemu-devel] [PULL 13/13] linux-user: implement renameat2

se are functionally identical. Feel free to add my Reviewed-by: Palmer Dabbelt <pal...@sifive.com>

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

On Fri, 12 Jan 2018 00:09:16 PST (-0800), h...@lst.de wrote: On Fri, Jan 12, 2018 at 07:24:54AM +1300, Michael Clark wrote: I'm going to be restoring branches for bbl and riscv-linux that work again priv 1.9.1. There are still other emulators and RTL that support priv1.9.1. Folk will have

Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition

On Thu, 11 Jan 2018 09:55:36 PST (-0800), Michael Clark wrote: On Fri, Jan 12, 2018 at 3:37 AM, Richard Henderson < richard.hender...@linaro.org> wrote: On 01/10/2018 06:21 PM, Michael Clark wrote: > +static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > +

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

On Wed, 10 Jan 2018 23:58:12 PST (-0800), h...@lst.de wrote: On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 - RISC-V Instruction Set

Re: [Qemu-devel] [PATCH] linux-user: Implement renameat2 when defined

On Thu, 21 Dec 2017 06:01:25 PST (-0800), peter.mayd...@linaro.org wrote: On 20 December 2017 at 00:29, Palmer Dabbelt <pal...@dabbelt.com> wrote: +#if defined(TARGET_NR_renameat2) && defined(__NR_renameat2) +case TARGET_NR_renameat2: +{ +void *p2;

[Qemu-devel] [PATCH] linux-user: Implement renameat2 when defined

From: Palmer Dabbelt <pal...@sifive.com> The RISC-V Linux port was recently accept upstream and will be released as part of 4.15. While working on our glibc port I discovered that qemu's user-mode emulation doesn't support renameat2, which has replaced rename as part of the default syste

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