[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2

The following changes since commit 81a23caf47956778c5a5056ad656d1ef92bf9659: Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2020-02-10 17:08:51 +) are available in the Git repository at: g...@github.com:palmer-dabbelt/qemu.git

[PULL 1/5] riscv/virt: Add syscon reboot and poweroff DT nodes

Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 26 ++ 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c44b865959..6d682f8a78 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -182,11

[PULL 3/5] hw: rtc: Add Goldfish RTC device

Linux. For now, VM migration support is available but untested for Goldfish RTC device. It will be hardened in-future when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/rtc/Kconfig| 3 + hw

[PULL 2/5] riscv: Separate FPU register size from core register size in gdbstub [v2]

Packard [Palmer: This requires manually triggering a rebuild of riscv32-softmmu/gdbstub-xml.c] Signed-off-by: Palmer Dabbelt --- configure | 4 ++-- target/riscv/gdbstub.c | 20 +++- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/configure b

Re: [PATCH v2 07/35] target/riscv: Add the force HS exception mode

ISCVState *env, bool enable) +{ +if (!riscv_has_ext(env, RVH)) { +return; +} + +env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = >env; Reviewed-by: Palmer Dabbelt

Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number

On Wed, 29 Jan 2020 07:29:11 PST (-0800), Palmer Dabbelt wrote: > On Fri, 10 Jan 2020 07:52:05 GMT (+), bmeng...@gmail.com wrote: >> Hi Palmer, >> >> On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt >> wrote: >>> >>> On Thu, 21 Nov 2019 1

Re: [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5

On Fri, 31 Jan 2020 17:01:35 PST (-0800), Alistair Francis wrote: This patch series adds the RISC-V Hypervisor extension v0.5. This is the latest draft spec of the Hypervisor extension. The Hypervisor extension is disabled by default, so this series should result in no changes to anyone using

Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub [v2]

On Thu, 30 Jan 2020 14:13:16 PST (-0800), kei...@keithp.com wrote: Palmer Dabbelt writes: This isn't working for me. When I apply it on top of my for-master (which is very close to master), I get warning: while parsing target description (at line 1): Could not load XML document

Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub [v2]

On Tue, 28 Jan 2020 23:32:16 GMT (+), kei...@keithp.com wrote: The size of the FPU registers is dictated by the 'f' and 'd' features, not the core processor register size. Processors with the 'd' feature have 64-bit FPU registers. Processors without the 'd' feature but with the 'f' feature

Re: [PATCH v2] riscv/virt: Add syscon reboot and poweroff DT nodes

ell(fdt, nodename, "regmap", test_phandle); +qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); +qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS); g_free(nodename); nodename = g_strdup_printf("/uart@%lx", Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers

On Tue, 21 Jan 2020 11:02:01 GMT (+), alistai...@gmail.com wrote: On Wed, Jan 8, 2020 at 11:30 AM Palmer Dabbelt wrote: On Mon, 09 Dec 2019 10:11:19 PST (-0800), Alistair Francis wrote: > To handle the new Hypervisor CSR register aliasing let's use pointers. For some reason I thought

Re: [PATCH v2 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation

On Wed, 22 Jan 2020 11:30:36 GMT (+), Anup Patel wrote: This patch extends CLINT emulation to provide rdtime callback for TCG. This rdtime callback will be called wheneven TIME CSRs are read in privileged modes. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis ---

Re: [PATCH v2 1/2] target/riscv: Emulate TIME CSRs for privileged mode

On Wed, 22 Jan 2020 11:30:31 GMT (+), Anup Patel wrote: Currently, TIME CSRs are emulated only for user-only mode. This patch add TIME CSRs emulation for privileged mode. For privileged mode, the TIME CSRs will return value provided by rdtime callback which is registered by QEMU

Re: [PATCH] riscv: Add semihosting support [v4]

On Thu, 30 Jan 2020 10:54:37 GMT (+), Peter Maydell wrote: On Wed, 29 Jan 2020 at 16:45, Keith Packard wrote: Peter Maydell writes: > True but irrelevant. You need to refer to a proper > risc-v specification for your semihosting. The RISC-V Foundation defined semihosting as relative to

Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number

On Fri, 10 Jan 2020 07:52:05 GMT (+), bmeng...@gmail.com wrote: Hi Palmer, On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt wrote: On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng...@gmail.com wrote: > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng wrote: >> >> At present t

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

On Fri, 24 Jan 2020 04:35:14 PST (-0800), Peter Maydell wrote: On Thu, 23 Jan 2020 at 18:43, Palmer Dabbelt wrote: On Thu, 23 Jan 2020 06:38:07 PST (-0800), Peter Maydell wrote: > Hi. This pull request doesn't seem to be signed with the GPG > key that I have on record for you... When I

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

On Thu, 23 Jan 2020 06:38:07 PST (-0800), Peter Maydell wrote: On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt wrote: The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e: ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +

[PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state

From: ShihPo Hung Signed-off-by: ShihPo Hung Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvd.inc.c | 1 - target/riscv/insn_trans/trans_rvf.inc.c | 1 - 2 files changed, 2 deletions(-) diff --git a/target

[PULL 3/5] target/riscv: Fix tb->flags FS status

ard Henderson Signed-off-by: ShihPo Hung Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c..de0a8d893a 100644 --- a/target/riscv/cpu.h ++

[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e: ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +) are available in the Git repository at: g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1 for you to

[PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize()

From: Pan Nengyuan Fix a minor memory leak in riscv_sifive_u_soc_realize() Reported-by: Euler Robot Signed-off-by: Pan Nengyuan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 1 + 1 file changed, 1 insertion

[PULL 2/5] riscv: Set xPIE to 1 after xRET

Francis Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 331cc36232..e87c9115bc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -93,7

[PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty

From: ShihPo Hung remove the check becuase SD bit should summarize FS and XS fields unconditionally. Signed-off-by: ShihPo Hung Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 3 +-- target/riscv/translate.c | 2

Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting

On Wed, 08 Jan 2020 18:33:40 PST (-0800), richard.hender...@linaro.org wrote: On 1/9/20 11:49 AM, Palmer Dabbelt wrote: +    irqs = (pending & ~env->mideleg & -mie) | (pending &  env->mideleg & -sie); Isn't "-unsigned" implementation defined?  I

Re: [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()

On Tue, 10 Dec 2019 10:38:29 PST (-0800), alistai...@gmail.com wrote: On Mon, Dec 9, 2019 at 11:15 PM wrote: From: Pan Nengyuan Fix a minor memory leak in riscv_sifive_u_soc_realize() Reported-by: Euler Robot Signed-off-by: Pan Nengyuan Reviewed-by: Alistair Francis Thanks. This is

Re: [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro

ctx->virt_enabled = true; } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR

arget_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) get_field(mstatus, MSTATUS_MPIE)); mstatus = set_field(mstatus, MSTATUS_MPIE, 1); mstatus = set_field(mstatus, MSTATUS_MPP, 0); +#ifdef TARGET_RISCV32 +*env->mstatush = set_field(*env->mstatush, MSTATUS_MPV, 0); +#else mstatus = set_field(mstatus, MSTATUS_MPV, 0); +#endif *env->mstatus = mstatus; riscv_cpu_set_mode(env, prev_priv); Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails

} else { +cs->exception_index = page_fault_exceptions ? +RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; +} break; default: g_assert_not_reached(); Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions

*cs) env->mcause = cause | ~(((target_ulong)-1) >> async); env->mepc = env->pc; env->mbadaddr = tval; +env->mtval2 = mtval2; env->pc = (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 31/36] target/riscv: Implement second stage MMU

true; } + if (ret == TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); @@ -631,9 +783,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else if (probe) { return false; } else { -raise_mmu_exception(env, address, access_type, pmp_violation, true); +raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error); riscv_raise_exception(env, cs->exception_index, retaddr); } + +return true; + #else switch (access_type) { case MMU_INST_FETCH: Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 30/36] target/riscv: Allow specifying MMU stage

se if (probe) { return false; } else { -raise_mmu_exception(env, address, access_type, pmp_violation); +raise_mmu_exception(env, address, access_type, pmp_violation, true); riscv_raise_exception(env, cs->exception_index, retaddr); } #else Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops

nabled = true; +} +} else { +ctx->virt_enabled = false; +} #else ctx->virt_enabled = false; #endif Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation

<< 1 & env->mideleg); +ret &= vsip_writable_mask; +ret >>= 1; +} else { +ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); +} + *ret_value &= env->

Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting

return ctz64(pending_hs_irq); +} + +pending = vspending; +} + +irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); Isn't "-unsigned" implementation defined? I can't get GCC to throw a warning and it was already there, so maybe I'm just wrong? if (irqs) { return ctz64(irqs); /* since non-zero */ Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 26/36] target/riscv: Remove the hret instruction

/insn_trans/trans_privileged.inc.c @@ -58,11 +58,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) #endif } -static bool trans_hret(DisasContext *ctx, arg_hret *a) -{ -return false; -} - static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY Reviewed-by: Palmer

Re: [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation

_INTERRUPTS) | (val & S_MODE_INTERRUPTS); +} + return write_mie(env, CSR_MIE, newval); } Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 16/36] target/riscv: Add virtual register swapping function

= env->sbadaddr; +env->sbadaddr = env->vstval; + +env->satp_hs = env->satp; +env->satp = env->vsatp; +} +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { Modulo that question about the concept of pointer swapping on the previous patch: Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension

s_ext(env, RVH)) { +env->mideleg |= VS_MODE_INTERRUPTS; +} return 0; } Do you have any idea why? The spec is explicit that this is the case, but I'm surprised. Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers

On Mon, 09 Dec 2019 10:11:19 PST (-0800), Alistair Francis wrote: To handle the new Hypervisor CSR register aliasing let's use pointers. For some reason I thought we were making this explicit? In other words, requiring that all callers provide which privilege mode they're using when accessing

Re: [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses

y Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions

pcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode

tive_priv++; } -if (write_mask && read_only) { + +if ((write_mask && read_only) || +(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { return -1; } #endif Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 07/36] target/riscv: Add the virtulisation mode

oid riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) +{ +if (!riscv_has_ext(env, RVH)) { +return; +} + +env->virt = set_field(env->virt, VIRT_ONOFF, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = >env; Reviewe

Re: [PATCH v1 05/36] target/riscv: Add support for the new execption numbers

T_PAGE_FAULT)) | +(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | +(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_SD; Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState

, +CSR_HTVAL, CSR_HIP, +CSR_HTINST, +CSR_HGATP, CSR_MBASE, CSR_MBOUND, CSR_MIBASE, Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs

<< IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) /* sip masks */ Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs

On Mon, 09 Dec 2019 10:10:45 PST (-0800), Alistair Francis wrote: Setting write permission on dirty PTEs results in userspace inside a Hypervisor guest (VU) becoming corrupted. This appears to be because it ends up with write permission in the second stage translation in cases where we aren't

Re: [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong

deleg ", env->mideleg); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c..f889427869 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,7 +121,7 @@ struct CPURISCVState { target_ulong mhartid; target_ulong mstatus; -uint32_t mip; +target_ulong mip; uint32_t miclaim; target_ulong mie; Reviewed-by: Palmer Dabbelt

[PULL 2/2] hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()

Spike board requires the access to locate the HTIF symbols. Fixes: 0ac24d56c5e7 ("hw/riscv: Split out the boot functions") Buglink: https://bugs.launchpad.net/qemu/+bug/1835827 Signed-off-by: Siwei Zhuang Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c

[PULL 1/2] RISC-V: virt: This is a "sifive,test1" test finisher

From: Palmer Dabbelt The test finisher implements the reset command, which means it's a "sifive,test1" device. This is a backwards compatible change, so it's also a "sifive,test0" device. I copied the odd idiom for adding a two-string compatible field from the AR

[PULL] RISC-V Patches for 4.2-rc3

that I'd like to target for 4.2-rc3: * A fix to the DT entry for the SiFive test finisher. * A fix to the spike board's HTIF interface. This passes "make check" and boots OE for me. -------- Palmer Dabbelt (1): RI

Re: [PATCH] riscv: virt: Allow PCI address 0

mc->init = riscv_virt_board_init; mc->max_cpus = 8; mc->default_cpu_type = VIRT_CPU; +mc->pci_allow_0_address = true; } static const TypeInfo riscv_virt_machine_typeinfo = { Reviewed-by: Palmer Dabbelt I've put this on for-next, as I don't think this is 4.2 material. Thanks!

Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number

ue for 5.0, with a Reviewed-by: Palmer Dabbelt Thanks!

Re: [PATCH] RISC-V: virt: This is a "sifive,test1" test finisher

On Thu, 21 Nov 2019 10:55:32 PST (-0800), alistai...@gmail.com wrote: On Wed, Nov 20, 2019 at 6:40 PM Palmer Dabbelt wrote: On Sun, 10 Nov 2019 13:10:33 PST (-0800), da...@gibson.dropbear.id.au wrote: > On Fri, Nov 08, 2019 at 10:13:16AM -0800, Palmer Dabbelt wrote: >> On Fri, 08 No

Re: [PATCH] RISC-V: virt: This is a "sifive,test1" test finisher

On Sun, 10 Nov 2019 13:10:33 PST (-0800), da...@gibson.dropbear.id.au wrote: On Fri, Nov 08, 2019 at 10:13:16AM -0800, Palmer Dabbelt wrote: On Fri, 08 Nov 2019 10:04:47 PST (-0800), Peter Maydell wrote: > On Fri, 8 Nov 2019 at 17:15, Alistair Francis wrote: > > > > On Fri, N

[PULL 4/4] riscv/virt: Increase flash size

that is 32MB. No QEMU release has include flash in the RISC-V virt machine, so this isn't a breaking change. Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

[PULL 2/4] target/riscv: Remove atomic accesses to MIP CSR

Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c| 5 ++-- target/riscv/cpu.h| 9 target/riscv/cpu_helper.c | 48 +++ target/riscv/csr.c| 2 +- 4 files

[PULL 3/4] opensbi: Upgrade from v0.4 to v0.5

: do not use relocated _boot_status before it is valid Nylon Chen (3): firmware: Fix the loop condition of _wait_relocate_copy_done section platform: Add Andes AE350 initial support scripts: Add AE350 to platform list in the binary archive script Palmer Dabbelt (1): Include `

[PULL 1/4] remove unnecessary ifdef TARGET_RISCV64

From: "hiroyuki.obinata" Signed-off-by: Hiroyuki Obinata Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b26533d4fd78..ab6a891dc381 100644 --

[PULL] RISC-V Fixes for 4.2-rc2

The following changes since commit aa464db69b40b4b695be31085e6d2f1e90956c89: Update version for v4.2.0-rc1 release (2019-11-12 18:40:02 +) are available in the Git repository at: g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-rc2 for you to fetch changes up to

[PATCH v2 3/3] RISC-V: virt: This is a "sifive,test1" test finisher

The test finisher implements the reset command, which means it's a "sifive,test1" device. This is a backwards compatible change, so it's also a "sifive,test0" device. Fixes: 9a2551ed6f ("riscv: sifive_test: Add reset functionality") Signed-off-by: Palmer Dabbelt -

[PATCH v2 0/3] device_tree: Allow for and use string arrays [Was: RISC-V: virt: This is a "sifive, test1" test finisher]

Device trees commonly contain arrays of strings for compatible nodes. We recently extended the "sifive,test0" node in a backwards-compatible way, but QEMU didn't contain an FDT function to set 'compatible = "sifive,test1", "sifive,test0";'. I've converted over the code from the ARM virt board

[PATCH v2 2/3] ARM/virt: Use fdt_setprop_strings()

-by: Palmer Dabbelt --- hw/arm/virt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc2607..4dc00f54d5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -304,9 +304,8 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms

[PATCH v2 1/3] device_tree: Add a helper function for string arrays

, "string2"] is represeted as "string1\0string2\0". The DTB generated by this function is accepted by DTC and produces an array of strings, but I can't find any explicit line in the DT specification that defines how these are encoded. Signed-off-by: Palmer Dabbelt --- dev

Re: [PATCH] RISC-V: virt: This is a "sifive,test1" test finisher

On Fri, 08 Nov 2019 10:04:47 PST (-0800), Peter Maydell wrote: On Fri, 8 Nov 2019 at 17:15, Alistair Francis wrote: On Fri, Nov 8, 2019 at 9:05 AM Palmer Dabbelt wrote: > > The test finisher implements the reset command, which means it's a > "sifive,test1" device.

[PATCH] RISC-V: virt: This is a "sifive,test1" test finisher

("riscv: sifive_test: Add reset functionality") Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 23f340df19..74f2dce81c 100644 --- a/hw/risc

Re: [PATCH for 4.2 v1 1/1] riscv/virt: Increase flash size

] ={ 0x8000, 0x0 }, [VIRT_PCIE_MMIO] = { 0x4000,0x4000 }, [VIRT_PCIE_PIO] ={ 0x0300,0x0001 }, Reviewed-by: Palmer Dabbelt I'll include this in my next PR, which should be soon -- I was about to send it, but figure I should look at my email first :)

Re: [PATCH v8 0/3] RTC support for QEMU RISC-V virt machine

On Wed, 06 Nov 2019 03:56:29 PST (-0800), Anup Patel wrote: This series adds RTC device to QEMU RISC-V virt machine. We have selected Goldfish RTC device model for this. It's a pretty simple synthetic device with few MMIO registers and no dependency external clock. The driver for Goldfish RTC is

Re: Adding New, Unsupported ISA to Qemu

On Tue, 05 Nov 2019 08:42:53 PST (-0800), stefa...@gmail.com wrote: On Mon, Nov 04, 2019 at 11:50:11PM +, Hanson, Seth via wrote: I'm looking for in-depth documentation pertaining to how an unsupported 16 bit RISC ISA can be emulated in Qemu. I've referenced this:

Re: [PATCH v1 1/1] opensbi: Upgrade from v0.4 to v0.5

On Tue, 05 Nov 2019 11:23:39 PST (-0800), alistai...@gmail.com wrote: > On Tue, Oct 29, 2019 at 3:33 AM Alistair Francis wrote: >> >> On Mon, Oct 28, 2019 at 5:56 PM Palmer Dabbelt wrote: >> > >> > On Sat, 26 Oct 2019 01:46:45 PDT (-0700), phi...@redhat.com w

Re: [PATCH v5 0/2] RTC support for QEMU RISC-V virt machine

On Sat, 02 Nov 2019 03:37:42 PDT (-0700), Peter Maydell wrote: On Tue, 29 Oct 2019 at 13:25, Alistair Francis wrote: On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote: > > This series adds RTC device to QEMU RISC-V virt machine. We have > selected Goldfish RTC device model for this. It's a

Re: [PATCH v5 0/2] RTC support for QEMU RISC-V virt machine

On Fri, 01 Nov 2019 08:40:24 PDT (-0700), a...@brainfault.org wrote: On Tue, Oct 29, 2019 at 6:55 PM Alistair Francis wrote: On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote: > > This series adds RTC device to QEMU RISC-V virt machine. We have > selected Goldfish RTC device model for this.

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

On Tue, 29 Oct 2019 23:54:30 PDT (-0700), alistai...@gmail.com wrote: On Tue, Oct 29, 2019 at 4:14 PM Palmer Dabbelt wrote: On Tue, 29 Oct 2019 03:49:23 PDT (-0700), alistai...@gmail.com wrote: > On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis wrote: >> >> On Fri, Oct 18,

Re: [PATCH] remove unnecessary ifdef TARGET_RISCV64

64 -[3] = MO_TEQ, [6] = MO_TEUL, -#endif }; #endif Reviewed-by: Palmer Dabbelt This is a non-functional change (the code in question was already wrapped in an "#ifdef TARGET_RISCV64", so this internal one was redundant), so I'm happy to include it during the soft

[PULL] Update my MAINTAINERS file entry

The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b: Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/palmer-for-master

[PULL] MAINTAINERS: Change to my personal email address

I'm leaving SiFive in a bit less than two weeks, which means I'll be losing my @sifive email address. I don't have my new email address yet, so I'm switching over to my personal address. Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- MAINTAINERS

[PATCH] MAINTAINERS: Change to my personal email address

I'm leaving SiFive in a bit less than two weeks, which means I'll be losing my @sifive email address. I don't have my new email address yet, so I'm switching over to my personal address instead. Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 4 ++-- 1 file

[Bug 1850378] Re: RISC-V unreliable IPIs

Can you post a whole program that reproduces this? freedom-e-sdk will run bare-metal code on QEMU if you don't want to post the rest of the surrounding infrastructure. -- You received this bug notification because you are a member of qemu- devel-ml,

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

On Tue, 29 Oct 2019 03:49:23 PDT (-0700), alistai...@gmail.com wrote: On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis wrote: On Fri, Oct 18, 2019 at 9:51 AM Palmer Dabbelt wrote: > > On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote: > > Instead of relyin

Re: [PATCH v1 1/1] opensbi: Upgrade from v0.4 to v0.5

On Sat, 26 Oct 2019 01:46:45 PDT (-0700), phi...@redhat.com wrote: On Sat, Oct 26, 2019 at 10:45 AM Philippe Mathieu-Daudé wrote: Hi Alistair, On 10/26/19 1:15 AM, Alistair Francis wrote: > This release has: > Lot of critical fixes > Hypervisor extension support > SBI v0.2

[PULL 17/18] riscv/boot: Fix possible memory leak

-by: Richard Henderson Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2e92fb0680..7fee98d2f8 100644 --- a/hw/riscv

[PULL 18/18] target/riscv: PMP violation due to wrong size parameter

on the starting address of the range, as `addr - 1` is not in the range. In order to fix, we just assume that all bytes from addr to the end of the page will be accessed if the size is unknown. Signed-off-by: Dayeol Lee Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c

[PULL 12/18] riscv/virt: Add the PFlash CFI01 device

Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 86 + include/hw/riscv/virt.h | 3 ++ 3 files changed, 90 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fb19b2df3a

[PULL 15/18] target/riscv: Expose "priv" register for GDB for reads

Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- configure | 4 ++-- gdb-xml/riscv-32bit-virtual.xml | 11 +++ gdb-xml/riscv-64bit-virtual.xml | 11 +++ target/riscv/gdbstub.c | 23 +++ 4 files c

[PULL 11/18] riscv/virt: Manually define the machine

-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 30 -- include/hw/riscv/virt.h | 7 ++- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

[PULL 06/18] linux-user/riscv: Propagate fault address

environment structure. In case of memory faults store the exception address into `siginfo`. Signed-off-by: Giuseppe Musacchio Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- linux-user/riscv/cpu_loop.c | 3 ++- target/riscv/cpu_helper.c | 5 - 2 files changed, 6 insertions(+), 2

[PULL 10/18] riscv/sifive_u: Add the start-in-flash property

From: Alistair Francis Add a property that when set to true QEMU will jump from the ROM code to the start of flash memory instead of DRAM which is the default behaviour. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv

[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2

/mst/tags/for_upstream' into staging (2019-10-28 13:32:40 +) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf2 for you to fetch changes up to 9667e53573f907d4fcd6accff1c8fe525544b749: target/riscv: PMP violation due to wrong size

[PULL 13/18] riscv/virt: Jump to pflash if specified

From: Alistair Francis If the user supplied pflash to QEMU then change the reset code to jump to the pflash base address instead of the DRAM base address. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Tested-by: Bin Meng Signed-off-by: Palmer

[PULL 08/18] riscv/sifive_u: Add QSPI memory region

QEMU's -device loader command line option. In the future we can look at adding a model for the is25wp256 flash. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 8 include/hw/riscv/sifive_u.h | 1 + 2 files changed, 9

[PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory

returned to all enabled from a reset. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 16 include/hw/riscv/sifive_u.h | 1 + 2 files changed, 17 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv

[PULL 03/18] RISC-V: Implement cpu_do_transaction_failed

This converts our port over from cpu_do_unassigned_access to cpu_do_transaction_failed, as cpu_do_unassigned_access has been deprecated. Signed-off-by: Palmer Dabbelt Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer

[PULL 02/18] RISC-V: Handle bus errors in the page table walker

Dabbelt Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv

[PULL 16/18] target/riscv: Make the priv register writable by GDB

and M-mode. Signed-off-by: Jonathan Behrens Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index

[PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode

ff-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f767ad24be..974c9c20b5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c

[PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs

-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e8d8..cb5bfd3d50 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7

[PULL 09/18] riscv/sifive_u: Manually define the machine

From: Alistair Francis Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer

[PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node

Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 02dd76176e..1ac51e3632 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -270,6 +270,10 @@ static

[PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes

From: Bin Meng The "clock-frequency" property of cpu nodes isn't required. Drop it. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133031/ Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt ---

Re: [PATCH] target/riscv: PMP violation due to wrong size parameter

On Tue, 22 Oct 2019 14:21:29 PDT (-0700), day...@berkeley.edu wrote: riscv_cpu_tlb_fill() uses the `size` parameter to check PMP violation using pmp_hart_has_privs(). However, if the size is unknown (=0), the ending address will be `addr - 1` as it is `addr + size - 1` in `pmp_hart_has_privs()`.

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