On Thu, 17 Oct 2019 05:08:39 PDT (-0700), Peter Maydell wrote:
Ping? It would be nice to see this patch get into master
to silence the coverity errors.
Sorry, it looks like I dropped this. It's in my queue, I hope to submit a PR
soon.
thanks
-- PMM
On Thu, 3 Oct 2019 at 18:05, Alistair
On Tue, 15 Oct 2019 10:04:32 PDT (-0700), day...@berkeley.edu wrote:
Hi,
Could this patch go through?
If not please let me know so that I can fix.
Thank you!
Sorry, I dropped this one. It's in the patch queue now. We should also check
for size==0 in pmp_hart_has_privs(), as that won't
UART0_IRQ = 10,
+RTC_IRQ = 11,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
This is a wacky enum, but it's already there. I'm going to assume this patch
will get merged and then fix it later.
--
2.17.1
Reviewed-by: Palmer Dabbelt
Acked-by: P
On Tue, 15 Oct 2019 01:35:31 PDT (-0700), Anup Patel wrote:
This patch adds model for Google Goldfish virtual platform RTC device.
We will be adding Goldfish RTC device to the QEMU RISC-V virt machine
for providing real date-time to Guest Linux. The corresponding Linux
driver for Goldfish RTC
On Mon, 14 Oct 2019 08:45:26 PDT (-0700), jonat...@fintelia.io wrote:
This series adds a new "priv" virtual register that reports the current
privilege mode. This is helpful for debugging purposes because that information
is not actually available in any of the real CSRs.
The third patch in
On Mon, 14 Oct 2019 10:59:07 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Oct 14, 2019 at 4:20 AM Alex Bennée wrote:
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Reviewed-by: Alistair Francis
and
Acked-
On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote:
Instead of relying on atomics to access the MIP register let's update
our helper function to instead just lock the IO mutex thread before
writing. This follows the same concept as used in PPC for handling
interrupts
On Mon, 07 Oct 2019 11:05:33 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Oct 3, 2019 at 8:53 AM Palmer Dabbelt wrote:
On Fri, 23 Aug 2019 16:38:47 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu_help
ion_index = RISCV_EXCP_STORE_PAGE_FAULT;
break;
+default:
+g_assert_not_reached();
}
+env->badaddr = address;
cpu_loop_exit_restore(cs, retaddr);
#endif
}
Reviewed-by: Palmer Dabbelt
I fixed up your Author tag and added this to for-master. Thanks!
On Wed, 25 Sep 2019 17:14:21 PDT (-0700), guo...@kernel.org wrote:
From: Guo Ren
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39:
registers already did so). I
haven't actually tried to manifest a bug here, but as far as I can tell
the soft float stuff does set the invalid flag.
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvd.inc.c | 2 ++
target/riscv/insn_trans/trans_rvf.inc.c | 4
2 files changed, 6
ldq(cs->as, pte_addr,
attrs, );
translate.c:782:ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
gdbstub.c:328:env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
All of these look safe to me.
v2:
- Rebase on master
Palmer Dabbelt (2):
RISC-V: Handle bus errors in
On Fri, 20 Sep 2019 07:20:34 PDT (-0700), Peter Maydell wrote:
On Fri, 20 Sep 2019 at 15:17, Paolo Bonzini wrote:
I think it's simplest if all series (RISC-V, remove unassigned_access,
this one) go through the RISC-V tree.
I don't inherently object but IME the risc-v tree tends to move
On Fri, 20 Sep 2019 02:19:02 PDT (-0700), bmeng...@gmail.com wrote:
U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.
This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133033/
Signed-off-by: Bin Meng
On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Sep 27, 2019 at 12:57 AM Bin Meng wrote:
On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
wrote:
>
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of
clude/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a921079fbe..2656b43c58 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -57,6 +57,8 @@ typedef struct SiFiveUState {
void *fdt;
int fdt_size;
+
+bool start_in_flash;
} SiFiveUState;
enum {
Reviewed-by: Palmer Dabbelt
ext_h;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 16:38:58 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 6 ++
target/riscv/cpu.h| 7 +++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 7 +++
target/riscv/csr.c| 23
On Fri, 23 Aug 2019 16:39:00 PDT (-0700), Alistair Francis wrote:
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 11 +++
} else if (probe) {
return false;
} else {
-raise_mmu_exception(env, address, access_type, pmp_violation, true);
+raise_mmu_exception(env, address, access_type, pmp_violation,
first_stage_error);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
+
+return true;
+
#else
switch (access_type) {
case MMU_INST_FETCH:
Reviewed-by: Palmer Dabbelt
*physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1)))
<<
+ PGSHIFT;
+} else {
+*physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
+}
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 16:38:47 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 39 ++-
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
On Fri, 23 Aug 2019 16:38:44 PDT (-0700), Alistair Francis wrote:
Respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when performing
floating point operations when V=0.
I'm confused as to what this has to do with floating point.
Signed-off-by: Alistair Francis
---
G_USER_ONLY)
+ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+#else
+ctx->virt_enabled = false;
+#endif
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
Reviewed-by: Palmer Dabbelt
riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (*env->mstatus & MSTATUS_FS) {
+if (riscv_cpu_virt_enabled(env) && !(env->vsstatus & MSTATUS_FS)) {
+return false;
+}
return true;
}
Reviewed-by: Palmer Dabbelt
riscv_cpu_set_virt_enabled(env, prev_virt);
+}
return retpc;
}
Reviewed-by: Palmer Dabbelt
);
+return true;
+/* } */
+}
+#endif
+return false;
+}
Reviewed-by: Palmer Dabbelt
On Tue, 24 Sep 2019 11:29:25 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
On 19-06-17 16:52:44, Richard Henderson wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
ldq(cs->as, pte_addr,
attrs, );
translate.c:782:ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
gdbstub.c:328:env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
All of these look safe to me.
Palmer Dabbelt (2):
RISC-V: Handle bus errors in the page table walker
RI
On Tue, 17 Sep 2019 09:37:47 PDT (-0700), alistai...@gmail.com wrote:
On Tue, Sep 17, 2019 at 6:56 AM Peter Maydell wrote:
On Fri, 16 Aug 2019 at 09:57, Peter Maydell wrote:
>
> On Thu, 15 Aug 2019 at 23:17, Palmer Dabbelt wrote:
> > You're more than welcome to take them ove
On Thu, 19 Sep 2019 15:24:51 PDT (-0700), Alistair Francis wrote:
This series aims to improve the use of QEMU for developing boot code. It
does a few things:
- sifive_u machine:
- Adds a chunk of memory in the Flash area. This allows boot loaders
to use this memory. I can't find details
L)) |
-(1ULL << (RISCV_EXCP_S_ECALL)) |
-(1ULL << (RISCV_EXCP_H_ECALL)) |
+(1ULL << (RISCV_EXCP_VS_ECALL)) |
+(1ULL << (RISCV_EXCP_HS_ECALL)) |
(1ULL << (RISCV_EXCP_M_ECALL)) |
(1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
Reviewed-by: Palmer Dabbelt
From: Bin Meng
This adds a helper routine for finding firmware. It is currently
used only for "-bios default" case.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 22 +++---
include/hw/riscv/boot.h
It should use the csr_register_map in order to reach the
riscv_cpu_get_fflags callback.
Signed-off-by: KONRAD Frederic
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/g
From: Alistair Francis
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target
From: Bin Meng
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3
From: Alistair Francis
This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.
Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
ta
reg base
& size to the property encoding.
Tested with upstream U-Boot and Linux kernel MACB drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_u.c | 24
includ
e name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.
From: Atish Patra
Use both the generic register name and ABI name for the general purpose
registers and floating point registers.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 19
From: Bin Meng
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c
From: Bin Meng
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h
From: Bin Meng
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv64-sifive_u
ny more.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +---
include/hw/riscv/sifive_u.h | 3 +--
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/ri
gned based on the property value.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/riscv_hart.c | 3 ++-
include/hw/riscv/riscv_hart.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_ha
From: Bin Meng
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv
From: Bin Meng
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +++-
include/hw
From: Bin Meng
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw/riscv
Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/sifive_u_otp.c | 191
include/hw/riscv/sifive_u_otp.h | 80 +
3 files changed, 272 insertions(+)
create mode 100644 hw/riscv/sifive_u_otp.c
create mode
From: Bin Meng
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 7
From: Bin Meng
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 23
From: Bin Meng
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
hw/riscv/sifive_uart.c | 1
From: Bin Meng
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv
nctions.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 2 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 79 ++--
From: Bin Meng
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 8 +---
hw/riscv/sifive_test.c | 5 +++--
hw/riscv
From: Bin Meng
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
[Palmer: Set default CPUs to 2]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 -
include/hw/riscv/sifive_u.h | 2
heterogeneous harts.
The cpu nodes in the generated DTS have been updated as well.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 92 +++--
include/hw/riscv/sifive_u.h | 6 ++-
2 files changed
From: Bin Meng
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
hw/riscv
From: Bin Meng
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 --
hw/riscv/
the file header says the RISC-V hart array holds the state
of a heterogeneous array of RISC-V harts, which is not true.
Update the comment to mention homogeneous array of RISC-V harts.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/riscv_hart.c
From: Bin Meng
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e_prci.c | 2
From: Bin Meng
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c |
From: Bin Meng
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.h | 3 ++-
2 files
From: Bin Meng
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv
From: Bin Meng
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_e.c | 23 ---
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw
From: Bin Meng
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4
hw/riscv/spike.c| 1 -
hw/ri
From: Bin Meng
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv
From: Bin Meng
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
From: Bin Meng
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/virt.c | 24
From: Alistair Francis
Update the Hypervisor CSR addresses to match the v0.4 spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 35 ++-
1 file changed, 18 insertions(+), 17 deletions
lted in duplicated inclusion of "hw/hw.h".
Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less")
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
2 files changed, 2
From: Bin Meng
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng
Reviewed-by: Alistair
cis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c| 31 ++-
target/riscv/trace-events | 6 ++
2 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d836288cb4..d4f1007109 100644
--- a/target/ri
.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Christophe de Dinechin
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 6 +-
target/riscv/cpu_helper.c | 10 ++
target/riscv/csr.c| 20 +++-
3 files changed, 26
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Behrens
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 12
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed
.
Signed-off-by: Bin Meng
Acked-by: Dr. David Alan Gilbert
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hmp-commands-info.hx | 2 +-
target/riscv/Makefile.objs | 4 +
target/riscv/monitor.c | 229 +
3 files changed, 234 insertions
-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8313f2605e..ae5a16e636 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
From: Philippe Mathieu-Daudé
The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 3
The following changes since commit f8c3db33a5e863291182f8862ddf81618a7c6194:
target/sparc: Switch to do_transaction_failed() hook (2019-09-17 12:01:00
+0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1-v3
for you to fetch
with error -2
when trying to boot Linux.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index
From: Guenter Roeck
Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20 +-
It works for me.
Jonathan
On Sun, Sep 15, 2019 at 1:31 PM Palmer Dabbelt wrote:
On Sun, 15 Sep 2019 06:07:18 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Palmer,
>
> On Sun, Sep 15, 2019 at 3:00 AM Palmer Dabbelt
wrote:
>>
>> On Fri, 13 Sep 2019 08:25:21 PDT (-0700), bm
a test for this, as
I'm assuming there's a better way to do it.
Signed-off-by: Palmer Dabbelt
---
vl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/vl.c b/vl.c
index 630f5c5e9c..821a5d91c8 100644
--- a/vl.c
+++ b/vl.c
@@ -2487,7 +2487,7 @@ static MachineClass *machine_parse(c
On Sun, 15 Sep 2019 06:07:18 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Sun, Sep 15, 2019 at 3:00 AM Palmer Dabbelt wrote:
On Fri, 13 Sep 2019 08:25:21 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Palmer,
>
> On Fri, Sep 13, 2019 at 10:33 PM Palmer Dabbelt wrote:
>>
On Fri, 23 Aug 2019 16:38:29 PDT (-0700), Alistair Francis wrote:
When the PLIC generates an interrupt ensure we always set it for the SIP
CSR that corresponds to the HS (V=0) register.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_plic.c | 12 +++-
1 file changed, 11
mp;
-get_field(*env->mstatus, MSTATUS_TW)) {
+get_field(*env->mstatus, MSTATUS_TW)) ||
+riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
Reviewed-by: Palmer Dabbelt
(pending & env->mideleg & -sie);
+if (riscv_cpu_virt_enabled(env)) {
+target_ulong pending_hs_irq = hspending & -vsie;
+
+if (pending_hs_irq) {
+riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
+return ctz64(pending_hs_irq);
+}
+}
+
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
Reviewed-by: Palmer Dabbelt
env->virt |= enable << VIRT_MODE_SHIFT;
}
Reviewed-by: Palmer Dabbelt
On Fri, 13 Sep 2019 08:25:21 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Fri, Sep 13, 2019 at 10:33 PM Palmer Dabbelt wrote:
On Fri, 06 Sep 2019 09:20:05 PDT (-0700), bmeng...@gmail.com wrote:
> It is not useful if we only have one management CPU.
>
> Signed-off-by:
On Wed, 11 Sep 2019 15:43:29 PDT (-0700), richard.hender...@linaro.org wrote:
On 9/11/19 2:25 AM, liuzhiwei wrote:
@@ -873,7 +925,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
[CSR_FRM] =
On Wed, 11 Sep 2019 00:00:56 PDT (-0700), aleksandar.m.m...@gmail.com wrote:
11.09.2019. 08.35, "liuzhiwei" је написао/ла:
Features:
* support specification riscv-v-spec-0.7.1(
https://content.riscv.org/wp-content/uploads/2019/06/17.40-Vector_RISCV-20190611-Vectors.pdf
).
Hi, Zhivei.
The
result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
+ val, -1);
if (result == 0) {
return sizeof(target_ulong);
}
Reviewed-by: Palmer Dabbelt
I just tagged a fixed version of my PR, but I'll include this in the next one.
On Fri, 06 Sep 2019 09:20:05 PDT (-0700), bmeng...@gmail.com wrote:
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in
On Fri, 13 Sep 2019 02:17:32 PDT (-0700), Peter Maydell wrote:
On Wed, 11 Sep 2019 at 09:24, Palmer Dabbelt wrote:
The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1:
Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07'
into staging (2019
On Fri, 23 Aug 2019 16:38:18 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 24 ---
target/riscv/cpu_bits.h | 7
target/riscv/cpu_helper.c | 88 +++
3 files changed, 113 insertions(+), 6
From: Atish Patra
Use both the generic register name and ABI name for the general purpose
registers and floating point registers.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 19
From: Bin Meng
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv
reg base
& size to the property encoding.
Tested with upstream U-Boot and Linux kernel MACB drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_u.c | 24
includ
From: Alistair Francis
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target
e name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.
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