From: Bin Meng
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv
From: Alistair Francis
This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.
Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
ta
From: Bin Meng
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h
From: Bin Meng
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 23
From: Bin Meng
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv64-sifive_u
From: Bin Meng
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3
From: Bin Meng
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +++-
include/hw
heterogeneous harts.
The cpu nodes in the generated DTS have been updated as well.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 92 +++--
include/hw/riscv/sifive_u.h | 6 ++-
2 files changed
Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/sifive_u_otp.c | 191
include/hw/riscv/sifive_u_otp.h | 80 +
3 files changed, 272 insertions(+)
create mode 100644 hw/riscv/sifive_u_otp.c
create mode
ny more.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +---
include/hw/riscv/sifive_u.h | 3 +--
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/ri
From: Bin Meng
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e_prci.c | 2
the file header says the RISC-V hart array holds the state
of a heterogeneous array of RISC-V harts, which is not true.
Update the comment to mention homogeneous array of RISC-V harts.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/riscv_hart.c
From: Bin Meng
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 7
From: Bin Meng
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
hw/riscv
From: Bin Meng
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c
From: Bin Meng
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw/riscv
nctions.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 2 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 79 ++--
From: Bin Meng
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 +++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
From: Bin Meng
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv
From: Bin Meng
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c |
From: Bin Meng
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_e.c | 23 ---
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw
gned based on the property value.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/riscv_hart.c | 3 ++-
include/hw/riscv/riscv_hart.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_ha
From: Bin Meng
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
From: Bin Meng
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/virt.c | 24
lted in duplicated inclusion of "hw/hw.h".
Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less")
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
2 files changed, 2
From: Bin Meng
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 8 +---
hw/riscv/sifive_test.c | 5 +++--
hw/riscv
From: Bin Meng
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4
hw/riscv/spike.c| 1 -
hw/ri
From: Bin Meng
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
hw/riscv/sifive_uart.c | 1
From: Bin Meng
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng
Reviewed-by: Alistair
.
Signed-off-by: Bin Meng
Acked-by: Dr. David Alan Gilbert
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hmp-commands-info.hx | 2 +-
target/riscv/Makefile.objs | 4 +
target/riscv/monitor.c | 229 +
3 files changed, 234 insertions
From: Bin Meng
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 --
hw/riscv/
From: Bin Meng
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.h | 3 ++-
2 files
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Behrens
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 12
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed
From: Alistair Francis
Update the Hypervisor CSR addresses to match the v0.4 spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 35 ++-
1 file changed, 18 insertions(+), 17 deletions
From: Bin Meng
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv
From: Bin Meng
This adds a helper routine for finding firmware. It is currently
used only for "-bios default" case.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 22 +++---
include/hw/riscv/boot.h
From: Guenter Roeck
Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20 +-
From: Philippe Mathieu-Daudé
The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 3
.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Christophe de Dinechin
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 6 +-
target/riscv/cpu_helper.c | 10 ++
target/riscv/csr.c| 20 +++-
3 files changed, 26
cis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c| 31 ++-
target/riscv/trace-events | 6 ++
2 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d836288cb4..d4f1007109 100644
--- a/target/ri
with error -2
when trying to boot Linux.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index
target_ulong mstatus = env->mstatus;
+target_ulong mstatus = *env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
@@ -121,7 +121,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
-env->mstatus = mstatus;
+*env->mstatus = mstatus;
return retpc;
}
@@ -132,7 +132,7 @@ void helper_wfi(CPURISCVState *env)
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
-get_field(env->mstatus, MSTATUS_TW)) {
+get_field(*env->mstatus, MSTATUS_TW)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
@@ -147,7 +147,7 @@ void helper_tlb_flush(CPURISCVState *env)
if (!(env->priv >= PRV_S) ||
(env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TVM))) {
+ get_field(*env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
I don't think this is that bad.
Reviewed-by: Palmer Dabbelt
-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8313f2605e..ae5a16e636 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1:
Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07'
into staging (2019-09-09 09:48:34 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv
+[CSR_VSATP] = { hmode, read_vsatp, write_vsatp
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
Reviewed-by: Palmer Dabbelt
;
+target_ulong vsatp;
+
target_ulong scounteren;
target_ulong mcounteren;
Reviewed-by: Palmer Dabbelt
);
+CPURISCVState *env = >env;
+#endif
+
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+#ifndef CONFIG_USER_ONLY
+qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv,
env->virt);
+#endif
log_target_disas(cpu, dcbase-&g
write_hgatp
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
Reviewed-by: Palmer Dabbelt
%s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
+if (riscv_has_ext(env, RVH)) {
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
+}
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc", env->mepc);
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc", env->sepc);
+if (riscv_has_ext(env, RVH)) {
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
+}
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
+if (riscv_has_ext(env, RVH)) {
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
+}
#endif
for (i = 0; i < 32; i++) {
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 16:38:00 PDT (-0700), Alistair Francis wrote:
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
On Fri, 23 Aug 2019 16:37:57 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
There's really no description of what this does, either in the commit message
or as a comment.
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h | 6 ++
cv_has_ext(env, RVH)) {
+return;
+}
+
+env->virt &= ~VIRT_MODE_MASK;
+env->virt |= enable << VIRT_MODE_SHIFT;
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = >env;
Reviewed-by: Palmer Dabbelt
/cpu.h
@@ -67,6 +67,7 @@
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
+#define RVH RV('H')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 08:21:06 PDT (-0700), Alistair Francis wrote:
The first three patches are ones that I have pulled out of my original
Hypervisor series at an attempt to reduce the number of patches in the
series.
These three patches all make sense without the Hypervisor series so can
be
|= env->mstatus & MSTATUS_FS;
+*flags |= TB_FLAGS_MSTATUS_FS;
I thought this was a functional change, but it's not: fp_enabled() checks
mstatus already.
}
#endif
}
Reviewed-by: Palmer Dabbelt
mmio;
+uint32_t hfxosccfg;
+uint32_t corepllcfg0;
+uint32_t ddrpllcfg0;
+uint32_t ddrpllcfg1;
+uint32_t gemgxlpllcfg0;
+uint32_t gemgxlpllcfg1;
+uint32_t coreclksel;
+uint32_t devicesreset;
+uint32_t clkmuxstatus;
+} SiFiveUPRCIState;
+
+#endif /* HW_SIFIVE_U_PRCI_H */
Reviewed-by: Palmer Dabbelt
include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "target/riscv/cpu.h"
Revieweb-by: Palmer Dabbelt
On Thu, 05 Sep 2019 08:57:44 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Thu, Sep 5, 2019 at 11:55 PM Bin Meng wrote:
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
---
Changes
On Thu, 05 Sep 2019 08:25:46 PDT (-0700), bmeng...@gmail.com wrote:
Hi Alistair,
On Thu, Sep 5, 2019 at 3:50 AM Alistair Francis wrote:
On Sat, Aug 31, 2019 at 7:54 PM Bin Meng wrote:
>
> As of today, the QEMU 'sifive_u' machine is a special target that does
> not boot the upstream
On Tue, 03 Sep 2019 20:41:52 PDT (-0700), bmeng...@gmail.com wrote:
Palmer,
On Wed, Aug 14, 2019 at 5:34 PM Bin Meng wrote:
Hi Palmer,
On Wed, Aug 7, 2019 at 10:53 AM Bin Meng wrote:
>
> On Wed, Aug 7, 2019 at 5:06 AM Philippe Mathieu-Daudé
wrote:
> >
> > On 8/5/19 8:43 AM, Bin Meng
On Tue, 27 Aug 2019 18:31:18 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Wed, Aug 28, 2019 at 7:18 AM Palmer Dabbelt wrote:
On Sun, 18 Aug 2019 22:59:54 PDT (-0700), bmeng...@gmail.com wrote:
> On Wed, Aug 14, 2019 at 11:33 PM Bin Meng wrote:
>>
>> This adds 'in
On Thu, 22 Aug 2019 15:37:15 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Aug 21, 2019 at 6:56 PM liuzhiwei wrote:
On 2019/8/22 上午3:31, Palmer Dabbelt wrote:
> On Thu, 15 Aug 2019 14:37:52 PDT (-0700), alistai...@gmail.com wrote:
>> On Thu, Aug 15, 2019 at 2:07 AM Peter Maydell
On Sun, 18 Aug 2019 23:00:40 PDT (-0700), bmeng...@gmail.com wrote:
On Wed, Aug 14, 2019 at 5:46 PM Bin Meng wrote:
Hi Palmer,
On Sat, Aug 10, 2019 at 9:49 AM Alistair Francis wrote:
>
> On Wed, Aug 7, 2019 at 7:50 PM Bin Meng wrote:
> >
> > For RV32, the root page table's PPN has 22 bits
all contiguous physical address mappings into
one block and only shows the merged block mapping details.
Signed-off-by: Bin Meng
Acked-by: Dr. David Alan Gilbert
Reviewed-by: Palmer Dabbelt
---
Changes in v4:
- restore to v2, that does not print all harts's PTE, since we
should switch
On Fri, 16 Aug 2019 06:09:34 PDT (-0700), bmeng...@gmail.com wrote:
Currently when QEMU is given a bios image with only a file name and
its file path passed in "-L", it still reports file not found.
This series fixes the issue. This is especially helpful for creating
distro QEMU packages.
Bin
On Thu, 15 Aug 2019 14:37:52 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Aug 15, 2019 at 2:07 AM Peter Maydell wrote:
On Thu, 15 Aug 2019 at 09:53, Aleksandar Markovic
wrote:
>
> > We can accept draft
> > extensions in QEMU as long as they are disabled by default.
> Hi, Alistair,
On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonat...@fintelia.io wrote:
Ping! What is the status of this patch?
Sorry, I must have lost track of it. I've added it to my patch queue.
On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens
wrote:
Bin, that proposal proved to be somewhat more
On Thu, 15 Aug 2019 14:39:18 PDT (-0700), alistai...@gmail.com wrote:
On Tue, Aug 13, 2019 at 3:44 PM Palmer Dabbelt wrote:
On Thu, 01 Aug 2019 08:39:17 PDT (-0700), Peter Maydell wrote:
> On Wed, 3 Jul 2019 at 09:41, Palmer Dabbelt wrote:
>>
>> From: Michael Clark
>&g
On Wed, 14 Aug 2019 18:30:59 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Thu, Aug 15, 2019 at 1:06 AM Palmer Dabbelt wrote:
On Mon, 12 Aug 2019 16:48:00 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Palmer,
>
> On Tue, Aug 13, 2019 at 6:45 AM Palmer Dabbelt wrote:
>>
On Tue, 13 Aug 2019 10:06:58 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Aug 12, 2019 at 4:08 PM Palmer Dabbelt wrote:
On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
> From: Atish Patra
>
> As per the RISC-V spec, Floating Point registers are named as f0.
On Mon, 12 Aug 2019 16:48:00 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Tue, Aug 13, 2019 at 6:45 AM Palmer Dabbelt wrote:
On Fri, 19 Jul 2019 06:40:43 PDT (-0700), li...@roeck-us.net wrote:
> Add support for loading initrd with "-initrd "
> to the sifive_u machi
ug 6, 2019 at 1:04 AM Alistair Francis
wrote:
> > >
> > > On Fri, Aug 2, 2019 at 11:08 PM Bin Meng wrote:
> > > >
> > > > Currently the make rules are wrongly using qemu/virt opensbi image
> > > > for sifive_u machine. Correct it.
> > &g
and -helpers.h in cpu.h for the few
bits that are global.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
I just reviewed v1, but this also applies to v2:
Reviewed-by: Alistair Francis
Acked-by: Palmer Dabbelt
I'm assuming this are going in through another tree, along with the rest
the S and U extensions when formatting ISA strings.
This boots Linux on top of 4.1-rc3, which no longer has the U extension
in /proc/cpuinfo.
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/target/riscv
On Wed, 07 Aug 2019 10:54:52 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Aug 7, 2019 at 8:00 AM Palmer Dabbelt wrote:
The ISA strings we're providing from QEMU aren't actually legal RISC-V
ISA strings, as both the S and U extensions cannot exist as
single-letter extensions and must
On Thu, 01 Aug 2019 08:39:17 PDT (-0700), Peter Maydell wrote:
On Wed, 3 Jul 2019 at 09:41, Palmer Dabbelt wrote:
From: Michael Clark
This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.
Signed-off-by: Michael Clark
[Changes by AF
quot;);
+return;
+}
+
+if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+monitor_printf(mon, "S-mode MMU unavailable\n");
+return;
+}
+
+if (env->priv_ver < PRIV_VERSION_1_10_0) {
+monitor_printf(mon, "Privileged mode < 1.10 unsupported\
On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
From: Atish Patra
As per the RISC-V spec, Floating Point registers are named as f0..f31
so lets fix the register names accordingly.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 8
On Fri, 19 Jul 2019 06:40:43 PDT (-0700), li...@roeck-us.net wrote:
Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.
Signed-off-by: Guenter Roeck
---
hw/riscv/sifive_u.c | 20 +---
1 file changed, 17
_DIAGNOSTIC_AVAILABLE
-# pragma GCC diagnostic pop
-#endif
-
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
Acked-by: Palmer Dabbelt
I assume you're taking this along with the rest though your tree.
On Thu, Aug 1, 2019 at 7:58 AM Bin Meng wrote:
> On Thu, Aug 1, 2019 at 10:16 PM Richard Henderson
> wrote:
> >
> > On 7/31/19 6:53 PM, Bin Meng wrote:
> > > I am not sure how (idx * ptesize) could overflow. It represents the
> > > offset by a page table which is [0, 4096).
> >
> > You're
strips out the S and U extensions when
formatting ISA strings.
This boots Linux on top of 4.1-rc3, which no longer has the U extension
in /proc/cpuinfo.
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git
On Wed, 07 Aug 2019 09:41:17 PDT (-0700), Peter Maydell wrote:
On Wed, 7 Aug 2019 at 16:02, Palmer Dabbelt wrote:
The ISA strings we're providing from QEMU aren't actually legal RISC-V
ISA strings, as both the S and U extensions cannot exist as
single-letter extensions and must instead
On Wed, 07 Aug 2019 09:08:20 PDT (-0700), Peter Maydell wrote:
On Wed, 7 Aug 2019 at 16:02, Palmer Dabbelt wrote:
The ISA strings we're providing from QEMU aren't actually legal RISC-V
ISA strings, as both the S and U extensions cannot exist as
single-letter extensions and must instead
strips out the S and U extensions when
formatting ISA strings.
This boots Linux on top of 4.1-rc3, which no longer has the U extension
in /proc/cpuinfo.
Signed-off-by: Palmer Dabbelt
---
This is another late one, but I'd like to target it for 4.1 as we're
providing illegal ISA strings and I
On Mon, 22 Jul 2019 22:30:15 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Sat, Jul 20, 2019 at 9:47 AM Palmer Dabbelt wrote:
On Fri, 14 Jun 2019 08:15:51 PDT (-0700), bmeng...@gmail.com wrote:
> This adds a reset opcode for sifive_test device to trigger a system
> reset for t
From: Alistair Francis
Fix a typo in the warning message displayed to users, don't print the
message when running inside qtest and don't mention a specific QEMU
version for the deprecation.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
The following changes since commit bf8b024372bf8abf5a9f40bfa65eeefad23ff988:
Update version for v4.1.0-rc2 release (2019-07-23 18:28:08 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-rc3
for you to fetch changes up
On Mon, 22 Jul 2019 11:22:43 PDT (-0700), alistai...@gmail.com wrote:
On Sat, Jul 20, 2019 at 2:30 AM Philippe Mathieu-Daudé
wrote:
On 7/19/19 8:05 PM, Alistair Francis wrote:
> Fix a typo in the warning message displayed to users, don't print the
> message when running inside qtest and don't
lude/hw/riscv/sifive_test.h
@@ -34,7 +34,8 @@ typedef struct SiFiveTestState {
enum {
FINISHER_FAIL = 0x,
-FINISHER_PASS = 0x
+FINISHER_PASS = 0x,
+FINISHER_RESET = 0x
};
DeviceState *sifive_test_create(hwaddr addr);
Reviewed-by: Palmer Dabbelt
Sorry
ed-by: Guenter Roeck
Signed-off-by: Palmer Dabbelt
---
.gitmodules | 3 ++
LICENSE | 21
Makefile | 5 +-
pc-bios/README | 11 +
pc-bios/
The following changes since commit 0b18cfb8f1828c905139b54c8644b0d8f4aad879:
Update version for v4.1.0-rc1 release (2019-07-16 18:01:28 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-rc2
for you to fetch changes up
Reviewed-by: Guenter Roeck
Tested-by: Guenter Roeck
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 54 +
hw/riscv/sifive_u.c | 7 +++---
hw/riscv/virt.c | 11 ++---
include/hw/riscv/boot.h | 3 +++
qemu-deprecated.texi| 20
On Fri, 14 Jun 2019 08:15:51 PDT (-0700), bmeng...@gmail.com wrote:
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.h | 3 ++-
2 files changed, 6
On Tue, 09 Jul 2019 01:37:08 PDT (-0700), Peter Maydell wrote:
On Tue, 9 Jul 2019 at 09:35, Palmer Dabbelt wrote:
I haven't looked at the code yet, but as the last one was fine it's probably
OK. My only issue here is the timing: it's after the soft freeze so if I
understand correctly we're
On Mon, 08 Jul 2019 11:49:35 PDT (-0700), Alistair Francis wrote:
This series includes the OpenSBI firmware for QEMU RISC-V users.
To avoid breakages we have not changed the default behaviour of QEMU.
The plan is to change the default though, which is why an entry to the
qemu-deprecated.texi
On Thu, 27 Jun 2019 11:23:20 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/27/19 7:44 PM, Jonathan Behrens wrote:
I think this patch is slightly incorrect. If the PMP region is valid for
the size of the access, but not the rest of the page then a few lines down
in this function the
From: Alistair Francis
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c
]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 62 +--
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 59a9b0437a5f..d37312705516 100644
--- a/disas/riscv.c
+++ b/disas
-by: Palmer Dabbelt
---
hw/riscv/boot.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 883df49a0c65..ff023f42d01d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const
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