Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 26 ++
hw/riscv/sifive_u.c | 4
hw/riscv/virt.c | 4
include/hw/riscv/boot.h | 2 ++
4 files changed, 36 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0c8e72e455d7
From: Joel Sing
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.
Signed-off-by: Joel Sing
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Palmer
/sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
i
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e2120ac7a5d3..a416d5d08b4d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -344,6
From: "Wladimir J. van der Laan"
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-
ed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 32 +---
target/riscv/cpu.h | 2 --
2 files changed, 9 insertions(+), 25 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1689ffecf85f..6a54ebf10c62 100644
--- a/target/
From: Alistair Francis
Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ecc47cea35d..e2120ac7a5d3 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h
).
Signed-off-by: Alistair Francis
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 17 +++--
2 files
-by: Jim Wilson
Reviewed-by: Laurent Vivier
Signed-off-by: Palmer Dabbelt
---
linux-user/riscv/syscall_nr.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h
index dab6509e3ade..5c8728220994 100644
From: Alistair Francis
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
qemu-deprecated.texi | 8
1 file changed, 8 insertions(+)
diff --git a/qemu
From: Alistair Francis
Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ba1325f43533..1689ffecf85f 100644
--- a/target/riscv
ch in SiFiveESoCState, so instead we just include them within
the struct.
Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt
Suggested-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_e
From: Alistair Francis
Add support for the ratified RISC-V privledge spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
2 files
From: Alistair Francis
Add support for disabling/enabling the "Counters" extension.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 17 -
3 fil
e correct PMP access exceptions
trap values.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.
From: Bin Meng
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5944f4cb6607..958c7502a0e0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -258,11 +258,12 @@ bool
From: Hesham Almatary
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target
inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.
Signed-off-by: Dayeol Lee
Reviewed-by: Alistair Francis
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file
From: Hesham Almatary
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 +-
target/riscv/pmp.c| 6 +++---
target/riscv/pmp.h| 2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 16
3 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0632ac08cf35
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v3
for you to fetch changes up to 395fd69582a00b76a89c12d9c074055a9d207997:
hw/riscv: Extend the kernel loading support (2019-06-27 02:47:06 -0700)
RISC-V
From: Nathaniel Graff
Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 70 --
target/riscv/cpu.h | 11
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6f2b64422086..0632ac08cf35
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0bbfb7f48b79..a45b05ef8395 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv
From: Alistair Francis
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e2120ac7a5d3..a416d5d08b4d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -344,6
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ecc47cea35d..e2120ac7a5d3 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
From: Alistair Francis
Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
.gitmodules | 3 ++
Makefile
From: "Wladimir J. van der Laan"
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-
ed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 32 +---
target/riscv/cpu.h | 2 --
2 files changed, 9 insertions(+), 25 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1689ffecf85f..6a54ebf10c62 100644
--- a/target/
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 26 ++
hw/riscv/sifive_u.c | 4
hw/riscv/virt.c | 4
include/hw/riscv/boot.h | 2 ++
4 files changed, 36 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0c8e72e455d7
Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 49 +
hw/riscv/sifive_u.c | 7 +++---
hw/riscv/virt.c | 11 ++---
include/hw/riscv/boot.h | 3 +++
qemu-deprecated.texi| 20 +
5 files changed, 84 insertions(
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1
From: Alistair Francis
Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions
: Palmer Dabbelt
---
hw/riscv/boot.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 883df49a0c65..ff023f42d01d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const
/sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
i
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h
]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 62 +--
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 59a9b0437a5f..d37312705516 100644
--- a/disas/riscv.c
+++ b/disas
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0bbfb7f48b79..a45b05ef8395 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv
-by: Jim Wilson
Reviewed-by: Laurent Vivier
Signed-off-by: Palmer Dabbelt
---
linux-user/riscv/syscall_nr.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h
index dab6509e3ade..5c8728220994 100644
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ba1325f43533..1689ffecf85f 100644
--- a/target/riscv
).
Signed-off-by: Alistair Francis
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 17 +++--
2 files
From: Joel Sing
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.
Signed-off-by: Joel Sing
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Palmer
From: Hesham Almatary
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
From: Alistair Francis
Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer
From: Alistair Francis
Add support for disabling/enabling the "Counters" extension.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 17 -
3 fil
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5944f4cb6607..958c7502a0e0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -258,11 +258,12 @@ bool
From: Hesham Almatary
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target
ch in SiFiveESoCState, so instead we just include them within
the struct.
Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt
Suggested-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_e
From: Alistair Francis
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
qemu-deprecated.texi | 8
1 file changed, 8 insertions(+)
diff --git a/qemu
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 +-
target/riscv/pmp.c| 6 +++---
target/riscv/pmp.h| 2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper
From: Bin Meng
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v2
for you to fetch changes up to 56bf43fc565a2fa3e0a618ab45e1c82896d0782a:
hw/riscv: Load OpenSBI as the default firmware (2019-06-28 10:10:30 -0700)
RISC-V
From: Alistair Francis
Add support for the ratified RISC-V privledge spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
2 files
inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.
Signed-off-by: Dayeol Lee
Reviewed-by: Alistair Francis
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 16
3 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0632ac08cf35
e correct PMP access exceptions
trap values.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 70 --
target/riscv/cpu.h | 11
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6f2b64422086..0632ac08cf35
From: Nathaniel Graff
Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c
On Fri, 28 Jun 2019 09:15:03 PDT (-0700), Alistair Francis wrote:
---
roms/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/roms/Makefile b/roms/Makefile
index 562ed726fd..dc70fb5aea 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -179,7 +179,7 @@ opensbi64-virt:
On Fri, 28 Jun 2019 09:12:45 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Jun 28, 2019 at 2:47 AM Jonathan Cameron
wrote:
On Thu, 27 Jun 2019 08:20:10 -0700
Palmer Dabbelt wrote:
> From: Alistair Francis
>
> Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
&
On Thu, 27 Jun 2019 12:56:57 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Jun 26, 2019 at 1:25 AM Palmer Dabbelt wrote:
On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote:
> On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote:
>>
>> I just did some test
From: Alistair Francis
Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
.gitmodules | 3 ++
Makefile
From: "Wladimir J. van der Laan"
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-
-by: Jim Wilson
Reviewed-by: Laurent Vivier
Signed-off-by: Palmer Dabbelt
---
linux-user/riscv/syscall_nr.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h
index dab6509e3ade..5c8728220994 100644
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ba1325f43533..1689ffecf85f 100644
--- a/target/riscv
From: Alistair Francis
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
qemu-deprecated.texi | 8
1 file changed, 8 insertions(+)
diff --git a/qemu
: Palmer Dabbelt
---
hw/riscv/boot.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 883df49a0c65..ff023f42d01d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1
From: Hesham Almatary
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ecc47cea35d..e2120ac7a5d3 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 26 ++
hw/riscv/sifive_u.c | 4
hw/riscv/virt.c | 4
include/hw/riscv/boot.h | 2 ++
4 files changed, 36 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0c8e72e455d7
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h
Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 49 +
hw/riscv/sifive_u.c | 7 +++---
hw/riscv/virt.c | 11 ++---
include/hw/riscv/boot.h | 3 +++
qemu-deprecated.texi| 20 +
5 files changed, 84 insertions(
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e2120ac7a5d3..a416d5d08b4d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -344,6
From: Bin Meng
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5944f4cb6607..958c7502a0e0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -258,11 +258,12 @@ bool
From: Joel Sing
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.
Signed-off-by: Joel Sing
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Palmer
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 +-
target/riscv/pmp.c| 6 +++---
target/riscv/pmp.h| 2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper
From: Alistair Francis
Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions
]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 62 +--
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 59a9b0437a5f..d37312705516 100644
--- a/disas/riscv.c
+++ b/disas
From: Hesham Almatary
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target
ch in SiFiveESoCState, so instead we just include them within
the struct.
Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt
Suggested-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_e
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0bbfb7f48b79..a45b05ef8395 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv
e correct PMP access exceptions
trap values.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.
From: Alistair Francis
Add support for disabling/enabling the "Counters" extension.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 17 -
3 fil
From: Alistair Francis
Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer
From: Alistair Francis
Add support for the ratified RISC-V privledge spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
2 files
ed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 32 +---
target/riscv/cpu.h | 2 --
2 files changed, 9 insertions(+), 25 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1689ffecf85f..6a54ebf10c62 100644
--- a/target/
From: Alistair Francis
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c
/sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
i
).
Signed-off-by: Alistair Francis
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 17 +++--
2 files
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 16
3 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0632ac08cf35
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 70 --
target/riscv/cpu.h | 11
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6f2b64422086..0632ac08cf35
601 - 700 of 1193 matches
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