ping
On 2022/10/24 16:41, Qi Hu wrote:
In sequence:
---
lock negl -0x14(%rbp)
pushf
pop%rax
---
%rax will obtain the wrong value becasue the "lock neg" calculates the
wrong eflags. The "s->T0" is updated by the wrong value.
You can use this to do some test:
On 2022/10/24 05:02, Philippe Mathieu-Daudé wrote:
Typo "calculation" in subject.
Thanks for the reminder. It's my fault. I will send V3 to fix this typo.
Qi
On 22/10/22 08:12, Qi Hu wrote:
In sequence:
---
lock negl -0x14(%rbp)
pushf
pop %rax
---
%rax will obtain
unsigned test = 0x2363a;
__volatile__ char cond = 0;
asm(
"lock negl %0 \n\t"
"sets %1"
: "=m"(test), "=r"(cond)
:
:);
assert(cond & 1);
return 0;
}
---
Reported-by: Jinyang Shen
Co-Developed-by: Xuehai Chen
Signe
unsigned test = 0x2363a;
__volatile__ char cond = 0;
asm(
"lock negl %0 \n\t"
"sets %1"
: "=m"(test), "=r"(cond)
:
:);
assert(cond & 1);
return 0;
}
---
Reported-by: Jinyang Shen
Co-Developed-by: Xuehai Chen
Signed
unsigned test = 0x2363a;
__volatile__ char cond = 0;
asm(
"lock negl %0 \n\t"
"sets %1"
: "=m"(test), "=r"(cond)
:
:);
assert(cond & 1);
}
---
Reported-by: Jinyang Shen
Co-Developed-by: Xuehai Chen
Signed-off-by: Xuehai Chen
Si
AArch64 defines the TCG_TARGET_HAS_direct_jump. So the "else" block is
useless in the case of "INDEX_op_goto_tb" in function "tcg_out_op". Add
an assertion and delete these codes for clarity.
Suggested-by: WANG Xuerui
Signed-off-by: Qi Hu
---
tcg
nop
will be used by "tb_target_set_jump_target".
Cc: Richard Henderson
Signed-off-by: Qi Hu
---
Changes since v3:
- Fix the offset check error which is pointed by WANG Xuerui.
- Use TMP0 instead of T0.
- Remove useless block due to direct jump support.
- Add some assertions.
---
tcg/loo
nop
will be used by "tb_target_set_jump_target".
Signed-off-by: Qi Hu
---
tcg/loongarch64/tcg-target.c.inc | 56 +---
tcg/loongarch64/tcg-target.h | 5 ++-
2 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/tcg/loongarch64/tcg-targ
On 2022/10/14 02:52, Richard Henderson wrote:
On 10/13/22 20:01, Qi Hu wrote:
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch. Additionally, if instruction "B offset" can cover
nop
will be used by "tb_target_set_jump_target".
Signed-off-by: Qi Hu
---
tcg/loongarch64/tcg-target.c.inc | 53 +---
tcg/loongarch64/tcg-target.h | 3 +-
2 files changed, 49 insertions(+), 7 deletions(-)
diff --git a/tcg/loongarch64/tcg-targ
On 2022/10/12 19:34, WANG Xuerui wrote:
Hi,
Thanks for the improvement! Some room for improvement though...
On 2022/10/12 17:13, Qi Hu wrote:
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch
On 2022/10/12 17:41, WANG Xuerui wrote:
Hi,
On 2022/10/12 17:13, Qi Hu wrote:
Signed-off-by: Qi Hu
---
tcg/loongarch64/tcg-target.c.inc | 9 +
tcg/loongarch64/tcg-target.h | 4 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg
Signed-off-by: Qi Hu
---
tcg/loongarch64/tcg-target.c.inc | 9 +
tcg/loongarch64/tcg-target.h | 4 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index a3debf6da7..f5a214a17f 100644
--- a/tcg
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch. Additionally, if instruction "B offset" can cover the target
address, "tb_target_set_jmp_target" will only patch the "B of
Hi,
This patch series add neg tcg_op and direct jump support into loongarch tcg
backend.
Qi Hu (2):
tcg/loongarch64: Implement INDEX_op_neg_i{32,64}
tcg/loongarch64: Add direct jump support
tcg/loongarch64/tcg-insn-defs.c.inc | 3 ++
tcg/loongarch64/tcg-target.c.inc| 58
On 2022/9/19 19:45, gaosong wrote:
在 2022/9/17 下午6:12, Richard Henderson 写道:
On 9/17/22 11:12, gaosong wrote:
在 2022/9/17 下午4:59, Qi Hu 写道:
On 2022/9/17 15:59, Song Gao wrote:
div.d, div.du, div,w, div.wu, the LoongArch host if x/0 the
result is 0.
The message has a typo: "
On 2022/9/17 17:16, gaosong wrote:
在 2022/9/17 下午4:41, Qi Hu 写道:
On 2022/9/17 15:59, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/insn_trans
On 2022/9/17 15:59, Song Gao wrote:
div.d, div.du, div,w, div.wu, the LoongArch host if x/0 the result is 0.
The message has a typo: "div,w" => "div.w"
Also I don't know why we need to do this, since the manual say: "When
the divisor is 0, the result can be any value".
So we set the div
On 2022/9/17 15:59, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc
b/target/loongarch/insn_trans/trans_bit.c.inc
index 9337714ec4..33
write the globle "fcsr"). This causes the "fdiv" helper updates
the "fcsr" into mem, but "movfcsr2gr" does not load it from mem.
Reported-by: Feiyang Chen
Signed-off-by: Qi Hu
---
target/loongarch/helper.h | 64 +++
On 2022/8/5 02:23, Richard Henderson wrote:
On 8/4/22 10:29, Qi Hu wrote:
Signed-off-by: Qi Hu
---
disas.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/disas.c b/disas.c
index e31438f349..d44f46 100644
--- a/disas.c
+++ b/disas.c
@@ -176,6 +176,8 @@ static void
Signed-off-by: Qi Hu
---
disas.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/disas.c b/disas.c
index e31438f349..d44f46 100644
--- a/disas.c
+++ b/disas.c
@@ -176,6 +176,8 @@ static void initialize_debug_host(CPUDebug *s)
#else
#error unsupported RISC-V ABI
#endif
+#elif defined
The macros SET_FPU_* are used to set corresponding bits of fcsr.
Unfortunately it forgets to set the result and it causes fcsr's
"CAUSE" never being updated. This patch is to fix this bug.
Signed-off-by: Qi Hu
---
target/loongarch/cpu.h | 18 +++---
1 file changed
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