Re: Error : "cxl_pci 0000:0d:00.0: Failed to get interrupt for event Info log"

2023-04-21 Thread RAGHU H
Hi Jonathan, The log is from the upstream version. I have your repo, I can work on it if you provide some basic details like the commit ID. Regards Raghu On Fri, Apr 21, 2023 at 6:05 PM Jonathan Cameron wrote: > > On Thu, 20 Apr 2023 18:07:40 +0530 > RAGHU H wrote: > > > H

Error : "cxl_pci 0000:0d:00.0: Failed to get interrupt for event Info log"

2023-04-20 Thread RAGHU H
Hello, I am using qemu config listed in CXL documentation to emulate CXL device -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \ -object memory-backend-file,id=cxl-mem

Re: [PATCH v1 0/2] Update CXL documentation

2023-04-14 Thread RAGHU H
Thanks Jonathan! I assume it will be merged sometime later with your other patches in the 8.x version! On Thu, Apr 13, 2023 at 2:58 PM Jonathan Cameron wrote: > > On Thu, 6 Apr 2023 18:58:37 +0530 > Raghu H wrote: > > > Thanks Jonathan for quick review/comments on earlier p

[PATCH v1 0/2] Update CXL documentation

2023-04-06 Thread Raghu H
mainlined. Raghu H (2): docs/cxl: Remove incorrect CXL type 3 size parameter docs/cxl: Replace unsupported AARCH64 with x86_64 docs/system/devices/cxl.rst | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) base-commit: 7d0334e49111787ae19fbc8d29ff6e7347f0605e -- 2.34.1

[PATCH v2 1/2] docs/cxl: Remove incorrect CXL type 3 size parameter

2023-04-06 Thread Raghu H
cxl-type3 memory size is read directly from the provided memory backed end device. Remove non existent size option Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices

[PATCH v2 2/2] docs/cxl: Replace unsupported AARCH64 with x86_64

2023-04-06 Thread Raghu H
Currently Qemu CXL emulation support is not availabe on AARCH64 but its available with qemu x86_64 architecture, updating the document to reflect the supported platform. Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[PATCH v1 2/2] docs/cxl: Replace unsupported AARCH64 with x86_64

2023-04-06 Thread Raghu H
Currently Qemu CXL emulation support is not availabe on AARCH64 but its available with qemu x86_64 architecture, updating the document to reflect the supported platform. Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff

[PATCH v1 0/2] Update CXL documentation

2023-04-06 Thread Raghu H
mainlined. Raghu H (2): docs/cxl: Remove incorrect CXL type 3 size parameter docs/cxl: Replace unsupported AARCH64 with x86_64 docs/system/devices/cxl.rst | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) base-commit: 7d0334e49111787ae19fbc8d29ff6e7347f0605e -- 2.34.1

[PATCH v1 1/2] docs/cxl: Remove incorrect CXL type 3 size parameter

2023-04-06 Thread Raghu H
cxl-type3 memory size is read directly from the provided memory backed end device. Remove non existent size option Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices

[PATCH] docs:remove cxl3 device size

2023-04-05 Thread Raghu H
cxl device typ3 size is read from the memory backend device, removing the size option specified in cxl sample command. Updating sample command to reflect target architecture as x86_64. Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 14 +++--- 1 file changed, 7 insertions