ve or downgrade more references to N extension
(#674)")
commit b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak
Reviewed-by: Andrew Jones
---
disas/riscv.c | 2 --
target/riscv/cpu_bits.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/d
XVentanaCondOps is Ventana custom extension. Add
its extension entry in the ISA Ext array
Signed-off-by: Rahul Pathak
---
This patch is based on branch riscv-to-apply.next (Alistair qemu tree)
Based on top commit: f2a91d8b78
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git
true, PRIV_VERSION_1_12_0, ext_svpbmt),
+ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
};
static bool isa_ext_is_enabled(RISCVCPU *cpu,
--
Thanks
Rahul
On Wed, Jul 27, 2022 at 12:26 PM Atish Patra wrote:
>
> The Sscofpmf ('Ss' for Privilege
Hi Alistair
My fix patch needs to be dropped since Anup took care of this issue
in his yesterdays series update in this patch -
[PATCH v8 4/4] target/riscv: Force disable extensions if priv spec
version does not match
Thanks
Rahul
On Wed, Jun 29, 2022 at 7:32 AM Alistair Francis wrote:
>
&
ce disable extensions if priv spec
version does not match")
Signed-off-by: Rahul Pathak
---
Changes in V2:
- remove the stray format specifier
- add the Fixes tag and reference to external tree
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c
ce disable extensions if priv spec
version does not match")
Signed-off-by: Rahul Pathak
---
Changes in V2:
- remove the stray format specifier
- add the Fixes tag and reference to external tree
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c
Sorry for spamming but my send-email script misbehaved
and sent the v2 patch two times. Please ignore one of
the v2 patch
On Mon, Jun 27, 2022 at 10:20 PM Rahul Pathak wrote:
>
> mhartid csr is not available in user-mode code path and
> user-mode build fails because of its ref
Hi Bin, Victor,
Going to send the v2 by fixing these
silly mistakes.
Thanks
Rahul
On Mon, Jun 27, 2022 at 7:59 PM Bin Meng wrote:
>
> On Mon, Jun 27, 2022 at 5:40 PM Rahul Pathak wrote:
> >
> > mhartid csr is not available in user-mode code path and
> > user-mode bu
mhartid csr is not available in user-mode code path and
user-mode build fails because of its reference in
riscv_cpu_realize function
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
On Wed, Oct 27, 2021 at 8:14 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:51 PM Rahul Pathak
> wrote:
> >
> > Patches add the mconfigptr csr support.
> > mconfigptr is newly incorporated in risc-v privileged architecture
> > specification 1.12 version
On Wed, Oct 27, 2021 at 8:08 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak
> wrote:
> >
> > Signed-off-by: Rahul Pathak
> > ---
> > target/riscv/cpu.c | 4 +++-
> > target/riscv/cpu.h | 1 +
> > 2 files changed, 4 inserti
On Wed, Oct 27, 2021 at 8:13 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak
> wrote:
> >
> > Signed-off-by: Rahul Pathak
> > ---
> > target/riscv/cpu_bits.h | 1 +
> > target/riscv/csr.c | 19 +++
>
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 4 +++-
target/riscv/cpu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 788fa0b11c..83c3814a5a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -405,7 +405,9
Signed-off-by: Rahul Pathak
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 19 +++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index cffcd3a5df..e2f154b7c5 100644
--- a/target/riscv/cpu_bits.h
ded privileged architecture spec version 1.12 ("v1.12.0") check
2. Added predicate function for mconfigptr which verifies
for priv spec version v1.12.0 or higher.
Thanks
Rahul
Rahul Pathak (2):
target/riscv: Add priv spec 1.12.0 version check
target/riscv: csr: Implement mconfigptr CSR
Hi Bin
On Thu, Oct 7, 2021 at 11:07 AM Bin Meng wrote:
>
> On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak wrote:
> >
> > mconfigptr is an mandatory CSR as per the priv spec.
>
> %s/an/a
>
Done
>
> as per the priv spec v1.12
>
> > This csr holds the phys
mconfigptr is an mandatory CSR as per the priv spec.
This csr holds the physical address of the configuration
data structure if this data structure is implemented
Its an readonly csr set to zero making configuration
data structure not supported.
Signed-off-by: Rahul Pathak
---
target/riscv
Hi Alistair,
One clarification: The unification of architectures is also going to allow
multi-arch CPUs (RV32/RV64) in a single machine instance? Or it's just
limited to only one in the runtime.
Rahul
On Tue, Sep 7, 2021 at 1:37 PM Ruinland ChuanTzu Tsai <
ruinl...@andestech.com> w
.sock.
I am unable to figure out what's wrong with unix\#serial1.sock
On Tue, Jun 1, 2021 at 7:48 PM Rahul Pathak
wrote:
> Hi Bin,
>
> Thanks for the response.
>
> I think the issue currently is that if I keep the "wait=on" and launch
> minicom on "unix\#seri
Hi Bin,
Thanks for the response.
I think the issue currently is that if I keep the "wait=on" and launch
minicom on "unix\#serial1.sock" then nothing happens.
Qemu keeps waiting for the connection on serial1 and no logs for uboot and
Kernel appears on the serial1.
Thanks
l=cadence_gem \
-nic tap,ifname=tap,model=cadence_gem,script=no \
-display none -serial stdio \
-chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
-serial chardev:serial1
Are there other ways in qemu icicle machine supported now to pass the
u-boot and kernel?
Thanks
Ra
On top of that, it seems I cannot connect with the target using gdb
(gdb) target remote :1234
Remote debugging using :1234
bfd requires flen 8, but target has flen 0
Though the ABI is lp64 and ISA is rv64imac when the hss was built.
On Mon, May 31, 2021 at 7:37 PM Rahul Pathak
wrote:
>
en if I remove the serial1 like in the second case.
Thanks
Rahul
On Mon, May 31, 2021 at 8:19 AM Bin Meng wrote:
> Hi Rahul,
>
> On Mon, May 31, 2021 at 1:08 AM Rahul Pathak
> wrote:
> >
> > Hi Bin,
> >
> > I was reading a github issue which you raised for the is
vice. However, I'm not sure if this
even makes sense in the case of I2C.
If this approach doesn't make sense, what method would you recommend to
have virtual I2C devices which are shared between multiple VMs?
Any suggestions or guidance is much appreciated!
Thanks in advance.
Sincerely,
Rahul Govind.
I am getting the following error while trying to compile the binaries for
QEMU emulator.
*GEN qemu.1qemu.pod around line 95: Non-ASCII character seen before
=encoding in 'Sch�tz.'. Assuming UTF-8POD document had syntax errors at
/usr/bin/pod2man line 68.Makefile:297: recipe for target 'qem
Plz co-ordinate with launchpad via bug we have created.
I need you to focus on this and get root cause by next week as per
postmortem.
-Rahul N.
On Saturday, April 14, 2012, arun gathiya wrote:
> found that there is patch available for this bug but the patch is for
Ubuntu 8.04.4 LTS(2.6.24
Plz co-ordinate with launchpad via bug we have created.
I need you to focus on this and get root cause by next week as per
postmortem.
-Rahul
On Saturday, April 14, 2012, arun gathiya wrote:
> found that there is patch available for this bug but the patch is for
Ubuntu 8.04.4 LTS(2.6.24-26)
Also FYI:
OS: Ubuntu 10.04
kernel: 2.6.32-28
-Rahul N.
On Wed, Apr 11, 2012 at 4:49 PM, Rahul Nair
wrote:
> Serge,
>
> This is a KVM base machine which faced the issue not a guest machine.
> In kern.log there was no Call Trace found during the time of issue.
> Also nothing wa
Serge,
This is a KVM base machine which faced the issue not a guest machine.
In kern.log there was no Call Trace found during the time of issue.
Also nothing was found in /var/crash/* too.
Are you aware of any possible reason due to which its not logged in any of
the log files?
-Rahul N.
On Tue
Were you able to find any clues...?
Rahul N.
On Tuesday, April 10, 2012, Rahul Nair wrote:
> Please check the attached screenshot that I took during the issue.
> I cant find anything useful in the logs.
>
> -Rahul N.
>
> On Tue, Apr 10, 2012 at 3:31 AM, Chris
Serge,
May be this screenshot (attached) will help.
-Rahul N.
On Tue, Apr 10, 2012 at 4:37 AM, Rahul Nair
wrote:
> Serge,
>
> These are the logs at the time when event occurred.
> But unfortunately nothing helpful was there in the logs.
> I am not sure about how can I provide
Please check the attached screenshot that I took during the issue.
I cant find anything useful in the logs.
-Rahul N.
On Tue, Apr 10, 2012 at 3:31 AM, Christopher M. Penalver <
christopher.penal...@gmx.com> wrote:
> rahul, thank you for reporting this and helping make Ubuntu better.
&g
Serge,
These are the logs at the time when event occurred.
But unfortunately nothing helpful was there in the logs.
I am not sure about how can I provide you the proper logs even if this
happened again.
-Rahul N.
On Tue, Apr 10, 2012 at 3:23 AM, Serge Hallyn
<977...@bugs.launchpad.net>
.12
-Rahul N.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/977391/+subscriptions
Serge,
I attaching the logs along with this mail.
-Rahul N.
On Tue, Apr 10, 2012 at 1:39 AM, Serge Hallyn
<977...@bugs.launchpad.net>wrote:
> Quoting Rahul (rahul.n...@finicity.com):
> > Is there any alternate way I can provide you the information?
> > I am actual
achine got hung up all of a sudden.
Not sure what exactly happened.
cat /proc/version_signature
Ubuntu 2.6.32-28.55-server 2.6.32.27+drm33.12
-Rahul N.
To manage notifications about this bug go to:
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