Blue Swirl wrote:
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints.
Signed-off-by: Blue Swirl
---
target-sparc/cpu.h |1 +
target-sparc/op_helper.c | 26 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target-sparc/cpu.h b
Blue Swirl wrote:
On Sat, Jan 22, 2011 at 3:30 PM, Mateusz Loskot wrote:
On 18/01/11 21:51, Blue Swirl wrote:
On Tue, Jan 18, 2011 at 6:00 PM, Mateusz Loskot wrote:
On 18/01/11 17:36, Blue Swirl wrote:
On Tue, Jan 18, 2011 at 3:27 PM, Mateusz Loskot
wrote:
Fix microSPARC II SFSR mask.
diff -p -u -r1.96 translate.c
--- target-sparc/translate.c5 Mar 2008 17:59:48 - 1.96
+++ target-sparc/translate.c6 Mar 2008 02:15:30 -
@@ -4259,7 +4259,7 @@ static const sparc_def_t sparc_defs[] =
.mmu_bm = 0x4000,
.mmu_ctpr
Remove unneeded qemu_irq_lower because user mode timers don't support
IRQs and the IRQ is lowered when switching to user mode.
diff -p -u -r1.30 slavio_timer.c
--- hw/slavio_timer.c 26 Jan 2008 09:13:46 - 1.30
+++ hw/slavio_timer.c 3 Mar 2008 00:35:28 -
@@ -192,7 +192,6 @@ static
Show which CPU IRQ is actually being set or reset when debugging.
diff -p -u -r1.86 sun4m.c
--- hw/sun4m.c 2 Mar 2008 08:48:47 - 1.86
+++ hw/sun4m.c 3 Mar 2008 00:35:29 -
@@ -258,12 +258,15 @@ void cpu_check_irqs(CPUState *env)
int old_interrupt = env->interrupt_in
Andrew Warkentin wrote:
SunOS might run in TME (http://people.csail.mit.edu/fredette/tme/). I
don't think anything other than Linux runs in QEMU's Sun emulation (or
for that matter, any of the non-PC QEMU emulators).
Unfortunately TME only emulates a SPARCstation2 (sun4c).
I have only bee
Jan Holzhueter wrote:
Hi everyone,
we are planing to get rid of some old sparc hardware.
The problem is that there are applications on it that require
sun4m and Solaris 1.1.2 / SunOS 4.1.4.
As known qemu-system-sparc is not able to boot the Solaris Kernel at
the moment.
I get as far as:
[spar
This patch gets openboot prom mmu register self tests passing for lx,
ss4, ss5 and ss10 prom images.
Index: target-sparc/cpu.h
===
RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v
retrieving revision 1.61
diff -p -u -r1.61 cpu.h
---
Blue Swirl wrote:
On 1/25/08, Robert Reif <[EMAIL PROTECTED]> wrote:
Blue Swirl wrote:
On 1/24/08, Robert Reif <[EMAIL PROTECTED]> wrote:
diff -p -u -r1.81 sun4m.c
This breaks my tests, so I guess a fix is also needed for OpenBIOS.
Probabl
Rediffed against cvs.
diff -p -u -r1.29 slavio_timer.c
--- hw/slavio_timer.c 25 Jan 2008 19:51:27 - 1.29
+++ hw/slavio_timer.c 25 Jan 2008 21:50:35 -
@@ -199,10 +199,8 @@ static void slavio_timer_mem_writel(void
count = ((uint64_t)s->counthigh << 32) | s->count;
Blue Swirl wrote:
On 1/23/08, Robert Reif <[EMAIL PROTECTED]> wrote:
Change ptimer limit only when mode changes.
Update timer configuration register user timer bits properly.
The patch does not apply.
It should apply on top of the first user timer patch that is in CVS now.
Blue Swirl wrote:
On 1/24/08, Robert Reif <[EMAIL PROTECTED]> wrote:
diff -p -u -r1.81 sun4m.c
This breaks my tests, so I guess a fix is also needed for OpenBIOS.
Probably, they were tested using ss5/170 and ss10 openboot images.
Exactly which version of gcc is this? It appears to work fine with at
least some gcc 3 versions.
gcc (GCC) 3.2.2 20030222 (Red Hat Linux 3.2.2-5)
Standard Red Hat 9.
diff -p -u -r1.81 sun4m.c
--- hw/sun4m.c 17 Jan 2008 21:04:16 - 1.81
+++ hw/sun4m.c 24 Jan 2008 05:06:38 -
@@ -687,7 +687,7 @@ static const struct hwdef hwdefs[] = {
.dma_base = 0x7840,
.esp_base = 0x7880,
.le_base = 0x78c0,
-
Thiemo Seufer wrote:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer08/01/23 19:01:12
Modified files:
. : cpu-all.h cpu-exec.c qemu-doc.texi vl.c
Log message:
Add option to disable TB cache, by Herve Poussineau.
CVSWeb URLs:
htt
Add microSPARC II and turboSPARC mask ID register support.
Index: hw/iommu.c
===
RCS file: /sources/qemu/qemu/hw/iommu.c,v
retrieving revision 1.25
diff -p -u -r1.25 iommu.c
--- hw/iommu.c 1 Jan 2008 17:06:38 - 1.25
+++ hw/
Change ptimer limit only when mode changes.
Update timer configuration register user timer bits properly.
--- hw/slavio_timer.c.old 2008-01-22 21:35:33.0 -0500
+++ hw/slavio_timer.c 2008-01-22 21:36:13.0 -0500
@@ -198,10 +198,8 @@ static void slavio_timer_mem_writel(void
Set limit bit when user timer expires.
Clear limit bit when user timer count set.
Set ptimer count when user timer count set.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.28
diff
Index: hw/eccmemctl.c
===
RCS file: /sources/qemu/qemu/hw/eccmemctl.c,v
retrieving revision 1.2
diff -p -u -r1.2 eccmemctl.c
--- hw/eccmemctl.c 1 Jan 2008 17:06:38 - 1.2
+++ hw/eccmemctl.c 6 Jan 2008 15:03:52 -000
Make these 3 error messages consistent with the other 20 in the same file.
diff -p -u -r1.79 sun4m.c
--- hw/sun4m.c 1 Jan 2008 20:57:25 - 1.79
+++ hw/sun4m.c 5 Jan 2008 22:26:07 -
@@ -385,7 +385,7 @@ static void sun4m_hw_init(const struct h
for(i = 0; i < smp_cpus; i++) {
This patch is trying to make qemu behave like real hardware. This is what
the OSs expect. The ability to create hardware that never existed and
can't
exist due to real hardware limitations is cool but it's not going to work
properly with existing OSs. At best you will have the OS never acces
Sun4m SMP machines support a maximum of 4 CPUs. Linux
knows this and uses fixed size arrays for per-cpu counter/timers
and interrupt controllers. Sun4m uni-processor machines use
the slaveio chip which has a single per-cpu counter/timer
and interrupt controller. However it does not fully decode
Paul Brook wrote:
What about a meaningful exit message?
"Out of memory" is a fairly comprehensive description of the problem.
In fact I'd say it's much more informative than "doesn't know or care about> failed to initialize".
If the user requested a target parameter that is beyond the
Paul Brook wrote:
s = (ptimer_state *)qemu_mallocz(sizeof(ptimer_state));
+if (!s)
+return NULL;
None of the callers bother to check the return value, And even if they did I
don't think there's any point trying to gracefully handle OOM. Just abort
and be done with it.
diff -p -u -r1.5 ptimer.c
--- hw/ptimer.c 17 Nov 2007 17:14:47 - 1.5
+++ hw/ptimer.c 3 Jan 2008 02:27:18 -
@@ -185,6 +185,8 @@ ptimer_state *ptimer_init(QEMUBH *bh)
ptimer_state *s;
s = (ptimer_state *)qemu_mallocz(sizeof(ptimer_state));
+if (!s)
+return NULL;
diff -p -u -r1.392 vl.c
--- vl.c28 Dec 2007 20:59:23 - 1.392
+++ vl.c3 Jan 2008 02:20:42 -
@@ -985,6 +985,8 @@ QEMUTimer *qemu_new_timer(QEMUClock *clo
QEMUTimer *ts;
ts = qemu_mallocz(sizeof(QEMUTimer));
+if (!ts)
+return NULL;
ts->clock
Paul Brook wrote:
On Wednesday 02 January 2008, Robert Reif wrote:
Sparc32 has a 64 bit counter that should be read and written as 64
bits but that isn't supported in QEMU. I did a quick hack to add
64 bit i/o and converted sparc32 to use it and it seems to work.
I'm suppling
Fix obio/power address for ss10 and ss20.
ss600mp doesn't have obio/power so fix slavio_misc to work without it.
Index: hw/slavio_misc.c
===
RCS file: /sources/qemu/qemu/hw/slavio_misc.c,v
retrieving revision 1.16
diff -p -u -r1.16 sl
diff -p -u -r1.73 sun4m.c
--- hw/sun4m.c 28 Dec 2007 20:59:23 - 1.73
+++ hw/sun4m.c 28 Dec 2007 21:25:06 -
@@ -698,7 +698,7 @@ static const struct hwdef hwdefs[] = {
.me_irq = 30,
.cs_irq = 5,
.machine_id = 0x80,
-.iommu_version = 0x0400,
+
Add asi debug info printing.
diff -p -u -r1.61 op_helper.c
--- target-sparc/op_helper.c10 Dec 2007 19:58:20 - 1.61
+++ target-sparc/op_helper.c28 Dec 2007 17:23:29 -
@@ -6,6 +6,7 @@
//#define DEBUG_MXCC
//#define DEBUG_UNALIGNED
//#define DEBUG_UNASSIGNED
+//#define DEBUG_A
Pass the asi number in is_asi. This works because asi 0 is not a valid asi.
Print out the type of access (read, write, exec).
diff -p -u -r1.61 op_helper.c
--- target-sparc/op_helper.c10 Dec 2007 19:58:20 - 1.61
+++ target-sparc/op_helper.c28 Dec 2007 17:07:49 -
@@ -416,7 +41
diff -p -u -r1.24 slavio_intctl.c
--- hw/slavio_intctl.c 17 Nov 2007 21:01:04 - 1.24
+++ hw/slavio_intctl.c 28 Dec 2007 01:46:54 -
@@ -145,7 +145,7 @@ static uint32_t slavio_intctlm_mem_readl
SLAVIO_INTCTLState *s = opaque;
uint32_t saddr, ret;
-saddr = (addr & INTC
This patch adds __func__ to 3 of the 4 debug printfs to make it
consistent with the the one that already uses it.
diff -p -u -r1.17 m48t59.c
--- hw/m48t59.c 17 Nov 2007 17:14:43 - 1.17
+++ hw/m48t59.c 27 Dec 2007 23:34:11 -
@@ -451,7 +451,7 @@ uint32_t m48t59_read (void *opaque, uint
All registers are set to 0 on reset.
This requires my prevoius patch which isn't in CVS yet.
diff -p -u -r1.23 slavio_timer.c
--- hw/slavio_timer.c 17 Dec 2007 18:21:57 - 1.23
+++ hw/slavio_timer.c 19 Dec 2007 12:28:30 -
@@ -306,13 +369,11 @@ static void slavio_timer_reset(void *
Fix count calculation when counter limit set to 0.
diff -p -u -r1.23 slavio_timer.c
--- hw/slavio_timer.c 17 Dec 2007 18:21:57 - 1.23
+++ hw/slavio_timer.c 18 Dec 2007 02:23:37 -
@@ -97,9 +97,14 @@ static int slavio_timer_is_user(SLAVIO_T
// Convert from ptimer countdown units
s
Set the proper limit when set to 0.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.21
diff -p -u -r1.21 slavio_timer.c
--- hw/slavio_timer.c 1 Dec 2007 15:58:22 - 1.21
+
Robert Reif wrote:
Only create as many per CPU timers as there are CPUs.
This time with the right patch.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.21
diff -p -u -r1.21
Only create as many per CPU timers as there are CPUs.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.21
diff -p -u -r1.21 slavio_timer.c
--- hw/slavio_timer.c 1 Dec 2007 15:58:22
Robert Reif wrote:
Characters written to serial port A are not reliably making it to the
screen.
Turning on serial debugging shows that the characters are written to the
serial port. The characters do make it to the screen when debugging.
The problem seems to be caused by multiple streams
Robert Reif wrote:
The problem I'm having is with sparc32 using a sun openboot image in
nographics mode where the prom uses serial port A as the system console.
The serial port output shows up in the host terminal window that qemu
was started in.
Characters written to serial port A ar
Blue Swirl wrote:
On 12/10/07, Robert Reif <[EMAIL PROTECTED]> wrote:
Writing data to a serial port on the sparc emulation happens immediately.
I would like to throttle the write speed to match the actual baud rate.
What's the best way to do this in qemu? Will QEMUTimer w
Writing data to a serial port on the sparc emulation happens immediately.
I would like to throttle the write speed to match the actual baud rate.
What's the best way to do this in qemu? Will QEMUTimer work for a
1 millisecond timer?
Index: vl.c
===
RCS file: /sources/qemu/qemu/vl.c,v
retrieving revision 1.377
diff -p -u -r1.377 vl.c
--- vl.c6 Dec 2007 22:11:20 - 1.377
+++ vl.c10 Dec 2007 01:17:59 -
@@ -7838,6 +7838,7 @@ static void
diff -p -u -r1.60 op_helper.c
--- target-sparc/op_helper.c28 Nov 2007 18:08:28 - 1.60
+++ target-sparc/op_helper.c9 Dec 2007 20:33:02 -
@@ -411,6 +411,9 @@ void helper_ld_asi(int asi, int size, in
break;
}
break;
+case 0x39: /* data cache di
* QEMU Sparc Sun4m ECC memory controller emulation
+ *
+ * Copyright (c) 2007 Robert Reif
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without re
Blue Swirl wrote:
On 12/4/07, Robert Reif <[EMAIL PROTECTED]> wrote:
I would be surprised if an SMP kernel actually worked on a multi CPU SS5.
Prepare for a surprise:
That's interesting because the fact that it works shows how inaccurate
the emulation is.
Now could
Blue Swirl wrote:
On 12/3/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch sets the maximum number of CPUs and memory to what is
supported by the actual hardware.
While it's not historically accurate to emulate a Sparcstation 5 with
16 CPUs and 2 gigabytes of memory,
If a sun system is booted without a keyboard, it uses serial port A for
the console.
This patch disables (unplugs) the keyboard when -nographic is set on the
command line.
Another option would be to add a -nokeyboard option to the command line.
Index: hw/slavio_serial.c
===
This patch sets the maximum number of CPUs and memory to what is
supported by the actual hardware.
Index: hw/sun4m.c
===
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.66
diff -p -u -r1.66 sun4m.c
--- hw/sun4m.c 2 De
Blue Swirl wrote:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/helper.c?cvsroot=qemu&r1=1.30&r2=1.31
Could you please set the mask to 0x7 for 512k proms.
Set initial value of AFSR register properly.
Index: hw/iommu.c
===
RCS file: /sources/qemu/qemu/hw/iommu.c,v
retrieving revision 1.19
diff -p -u -r1.19 iommu.c
--- hw/iommu.c 17 Nov 2007 17:14:42 - 1.19
+++ hw/iommu.c 21 No
This patch adds support for some more MMU registers:
0x10 TLB replacement control
0x13 read/write access to 0x03 SFSR
0x14 read/write access to 0x04 SFAR
Only support for 1 real register was added (0x10) but 16 were added
to CPUSPARCState because we don't check for invalid register
Blue Swirl wrote:
On 11/18/07, Robert Reif <[EMAIL PROTECTED]> wrote:
Blue Swirl wrote:
On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch fixes the word order for 64 bit reads of the mxcc registers.
Otherwise everything seems OK, b
Blue Swirl wrote:
On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch fixes the word order for 64 bit reads of the mxcc registers.
Otherwise everything seems OK, but it breaks NetBSD version 3 on SS10:
clock0 at obio0 slot 0 offset 0x20: mk48t08
timer0 at obio
Remove unnecessary masking of lower word with 0x.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- target-sparc/op_helper.c
Fix MXCC error register bit clearing.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- target-sparc/op_helper.c11 Nov 2007 19:46
This patch fixes the word order for 64 bit reads of the mxcc registers.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- targ
Add new MXCC register.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -r1.52 op_helper.c
209a210,217
> case 0x01c00c00: /* Module reset register */
>
Add iommu version to sparc32. Also reset iommu after initialization.
Should the version be tied to CPU model instead of machine type? At
least for Turbosparc this seems to be the case.
On SMP systems the IOMMU is on the system board in a separate ASIC. On
single CPU systems the IOM
This patch fixes the word order for 64 bit reads of the mxcc registers.
It returns the high 32 bits in ret and the lower 32 bits in T0 just
like other places in the same function.
T0 is defined as: register uint32_t T0 asm(AREG1);
T0 on my machine has a sizeof = 4. Because of this, I don't thi
Add iommu version to sparc32. Also reset iommu after initialization.
Index: hw/iommu.c
===
RCS file: /sources/qemu/qemu/hw/iommu.c,v
retrieving revision 1.17
diff -p -u -r1.17 iommu.c
--- hw/iommu.c 6 Oct 2007 11:28:21 - 1
Blue Swirl wrote:
DPRINTF_ASI would be nice.
Here is a revised patch:
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.51
diff -p -u -r1.51 op_helper.c
--- targe
This patch makes debugging asi and mxcc accesses easier to follow.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.51
diff -p -u -r1.51 op_helper.c
--- target-sparc/op_
This patch also performs a CPU reset after the CPU is registered rather
than before.
Why is this change needed?
Reset should be doing CPU dependent stuff and the CPU dependent setup
is performed when the CPU is registered.
This patch adds CPU dependent boot mode flag support.
Different CPUs use different bits for the boot mode flag. The constant
MMU_BM is replaced with a variable which is set for the selected CPU.
This patch also removes the MMU flags from being saved in the
translation block code as a result of
I'm looking at adding more complete support for different sparc32
CPUs, MMUs, cache controllers and systems.
Each CPU/MMU/cache controller combination is slightly different and
requires its own unique state. For example the two CPUs currently
supported save the boot mode in different bits in th
Please use this version. The previous version didn't mask off the top
address bit.
The sysctrl register is actually 32 bits. Add code to access it as 32
bits.
Index: hw/slavio_misc.c
===
RCS file: /sources/qemu/qemu/hw/slavio_
The sysctrl register is actually 32 bits. Add code to access it as 32 bits.
Index: hw/slavio_misc.c
===
RCS file: /sources/qemu/qemu/hw/slavio_misc.c,v
retrieving revision 1.10
diff -p -u -r1.10 slavio_misc.c
--- hw/slavio_misc.c
Blue Swirl wrote:
On 10/14/07, Robert Reif <[EMAIL PROTECTED]> wrote:
Should the address be 64 bit alligned? i.e. T0 & ~7 rather than T0 & ~3?
Should these unaligned address cause traps?
Yes, but the checks are already generated from translate.c
(gen_op_check_align_T0
Use stq_* for 64 bit stores.
This fixes one bug where T1 was used twice rather than T1 and T2.
Should the address be 64 bit alligned? i.e. T0 & ~7 rather than T0 & ~3?
Should these unaligned address cause traps?
Index: target-sparc/op_helper.c
=
Updated patch base of feedback.
This patch adds SuperSparc MXCC support.
DPRINTF_MMU and DPRINTF_MXCC added.
I decided not to use do_unassigned_access() at this time because I don't
know what real hardware does.
Index: hw/sun4m.c
=
Blue Swirl wrote:
On 10/13/07, Robert Reif <[EMAIL PROTECTED]> wrote:
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks?
I'm not sure what I'm doing is portable between 32/64
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks?
I'm not sure what I'm doing is portable between 32/64 and big/little endian.
Index: hw/sun4m.c
PPC compiling has been broken for me in CVS for a few days and is
getting worse.
I'm running Red Hat 9.
make -C i386-linux-user all
make[1]: Entering directory `/home/wine/qemu/i386-linux-user'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/wine/qemu/i386-linux-user'
mak
Some more user timer fixes.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.17
diff -p -u -r1.17 slavio_timer.c
--- hw/slavio_timer.c 6 Oct 2007 11:28:21 - 1.17
+++ hw/s
Add support to sparc for loading a real bios image.
Index: hw/sun4m.c
===
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.52
diff -p -u -r1.52 sun4m.c
--- hw/sun4m.c 5 Oct 2007 13:08:35 - 1.52
+++ hw/sun4m.
Sparc32 CVS exits after illegal instruction trap.
[H[JNvram id QEMU_BIOS, version 1, machine id 0x80
CPUs: 1
Welcome to OpenBIOS v1.0RC1 built on Aug 11 2007 08:00
Type 'help' for detailed information
[sparc] Kernel already loaded
qemu: fatal: Trap 0x02 while interrupts disabled, Error state
Increase size of PROM to match actual hardware.
Index: hw/sun4m.c
===
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.50
diff -p -u -r1.50 sun4m.c
--- hw/sun4m.c 24 Sep 2007 19:44:09 - 1.50
+++ hw/sun4m.c 30
With the patch and ss10 boot prom I get:
TIMER: write 000ff13c
TIMER: write 000ff1310010 0001
TIMER: write 000ff130
TIMER: write 000ff134
TIMER: write 000ff13c 0001
TIMER: write 000ff130
TIMER: write 000ff
I'm trying to run a real ss10 openboot prom image rather than
the supplied prom image and found some issues with the way
counters and timers are implemented. It appears that the processor
and system counter/timers are not independent. The system
config register actually configures the processor
I'm trying to use sparc32 on linux i686 RH9 and am unable to
to get this working with current CVS. My old scripts that
didn't set any networking options no longer work. When
running a debian sparc netinst cd the setup finds a dhcp
connection but is unable to connect to the internet.
Adding -use
It's been a few months since I comipled from source so I
just tried with current CVS and got these errors on RH9:
/home/wine/qemu/linux-user/syscall.c: In function `sys_tgkill':
/home/wine/qemu/linux-user/syscall.c:170: `__NR_tgkill' undeclared
(first use in this function)
/home/wine/qemu/linux-
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