Re: [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions

an Koppelmann wrote: > > On 09/26/2016 02:21 PM, Paolo Bonzini wrote: > >> > >> > >> On 26/09/2016 12:56, Sagar Karandikar wrote: > >>> +#ifndef CONFIG_USER_ONLY > >>> +DEF_HELPER_4(csrrw, tl, env, tl, tl, tl) > >>> +DEF_HEL

[Qemu-devel] [PATCH 11/18] target-riscv: Add Double Precision Floating-Point Instructions

Signed-off-by: Sagar Karandikar --- target-riscv/fpu_helper.c | 225 ++ target-riscv/helper.h | 30 +++ target-riscv/translate.c | 135 3 files changed, 390 insertions(+) diff --git a/target-riscv/fpu_helper.c b

[Qemu-devel] [PATCH 05/18] target-riscv: Add Arithmetic instructions

Arithmetic Instructions Arithmetic Immediate Instructions MULHSU Helper GPR Helpers necessary for above Signed-off-by: Sagar Karandikar --- target-riscv/helper.h| 4 + target-riscv/op_helper.c | 10 ++ target-riscv/translate.c | 338 +++ 3

[Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,

Along with FP helper infrastructure, changes to softfloat-specialize Signed-off-by: Sagar Karandikar --- fpu/softfloat-specialize.h | 7 ++- target-riscv/Makefile.objs | 2 +- target-riscv/fpu_helper.c | 151 + target-riscv/helper.h | 10

[Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/

Signed-off-by: Sagar Karandikar --- target-riscv/Makefile.objs | 1 + target-riscv/cpu.c | 154 ++ target-riscv/cpu.h | 497 + target-riscv/helper.c | 59 ++ target-riscv/helper.h | 0 target-riscv

[Qemu-devel] [PATCH 13/18] target-riscv: Add CSR read/write helpers

Signed-off-by: Sagar Karandikar --- target-riscv/op_helper.c | 324 +++ 1 file changed, 324 insertions(+) diff --git a/target-riscv/op_helper.c b/target-riscv/op_helper.c index ee51f02..8449d1b 100644 --- a/target-riscv/op_helper.c +++ b/target-riscv

[Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions

Signed-off-by: Sagar Karandikar --- target-riscv/fpu_helper.c | 206 ++ target-riscv/helper.h | 28 +++ target-riscv/translate.c | 146 3 files changed, 380 insertions(+) diff --git a/target-riscv

[Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode

Body of decode_opc with LUI, AUIPC, JAL instructions Decode table in instmap.h Signed-off-by: Sagar Karandikar --- target-riscv/instmap.h | 328 +++ target-riscv/translate.c | 64 + 2 files changed, 392 insertions(+) create mode 100644

[Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions

System instructions, stubs for csr read/write, necessary helpers Signed-off-by: Sagar Karandikar --- target-riscv/helper.h| 11 target-riscv/op_helper.c | 144 +++ target-riscv/translate.c | 119 +++ 3

[Qemu-devel] [PATCH 17/18] target-riscv: Add support for Host-Target Interface (HTIF) Devices

HTIF devices are currently used for the console and signaling test completion for tests in riscv-tests. These are not part of any RISC-V standard and will be phased out once better device support is available. Signed-off-by: Sagar Karandikar --- hw/riscv/Makefile.objs | 2 + hw/riscv

[Qemu-devel] [PATCH 18/18] target-riscv: Add generic test board, activate target

Signed-off-by: Sagar Karandikar --- configure | 6 + default-configs/riscv32-softmmu.mak | 38 ++ default-configs/riscv64-softmmu.mak | 38 ++ hw/riscv/Makefile.objs | 2 + hw/riscv/riscv_board.c | 264

[Qemu-devel] [PATCH 08/18] target-riscv: Add Atomic Instructions

Signed-off-by: Sagar Karandikar --- target-riscv/translate.c | 154 +++ 1 file changed, 154 insertions(+) diff --git a/target-riscv/translate.c b/target-riscv/translate.c index 767cdbe..af82eab 100644 --- a/target-riscv/translate.c +++ b/target-riscv

[Qemu-devel] [PATCH 14/18] target-riscv: softmmu/address translation support

Signed-off-by: Sagar Karandikar --- target-riscv/helper.c| 211 ++- target-riscv/op_helper.c | 29 +++ 2 files changed, 238 insertions(+), 2 deletions(-) diff --git a/target-riscv/helper.c b/target-riscv/helper.c index dfdc7bd..2e02351 100644

[Qemu-devel] [PATCH 16/18] target-riscv: Timer Support

Signed-off-by: Sagar Karandikar --- hw/riscv/Makefile.objs| 1 + hw/riscv/cpudevs.h| 17 +++ hw/riscv/riscv_rtc.c | 230 ++ include/hw/riscv/riscv_rtc.h | 25 include/hw/riscv

[Qemu-devel] [PATCH 07/18] target-riscv: Add Loads/Stores, FP Loads/Stores

Signed-off-by: Sagar Karandikar --- target-riscv/translate.c | 117 +++ 1 file changed, 117 insertions(+) diff --git a/target-riscv/translate.c b/target-riscv/translate.c index d8044cf..767cdbe 100644 --- a/target-riscv/translate.c +++ b/target-riscv

[Qemu-devel] [PATCH 03/18] target-riscv: Add initialization for translation

Add tcg and cpu model initialization Add gen_intermediate_code function, dummy decode_opc Add exception helpers necessary for gen_intermediate_code Signed-off-by: Sagar Karandikar --- target-riscv/helper.h| 4 + target-riscv/op_helper.c | 26 + target-riscv/translate.c | 244

[Qemu-devel] [PATCH 15/18] target-riscv: Interrupt Handling

Signed-off-by: Sagar Karandikar --- target-riscv/helper.c | 154 ++ 1 file changed, 154 insertions(+) diff --git a/target-riscv/helper.c b/target-riscv/helper.c index 2e02351..08c53fa 100644 --- a/target-riscv/helper.c +++ b/target-riscv/helper.c

[Qemu-devel] [PATCH 06/18] target-riscv: Add JALR, Branch Instructions

Signed-off-by: Sagar Karandikar --- target-riscv/translate.c | 107 +++ 1 file changed, 107 insertions(+) diff --git a/target-riscv/translate.c b/target-riscv/translate.c index ccfb795..d8044cf 100644 --- a/target-riscv/translate.c +++ b/target-riscv

[Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G)

riscv/riscv-isa-sim Sagar Karandikar (18): target-riscv: Add RISC-V target stubs and Maintainer target-riscv: Add RISC-V Target stubs inside target-riscv/ target-riscv: Add initialization for translation target-riscv: Add framework for instruction decode target-riscv: Add Arithmet

[Qemu-devel] [PATCH 01/18] target-riscv: Add RISC-V target stubs and Maintainer

Only files that live outside of target-riscv and hw/riscv, excluding configure and default-configs changes. Signed-off-by: Sagar Karandikar --- MAINTAINERS| 7 +++ arch_init.c| 2 ++ cpus.c | 6 ++ include/elf.h | 2

[Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)

v/riscv-isa-sim Sagar Karandikar (1): riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G) arch_init.c|2 + configure |